Commit d56a669c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'devicetree-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull second batch of devicetree updates from Rob Herring:
 "As Grant mentioned in the first devicetree pull request, here is the
  2nd batch of DT changes for 4.1.  The main remaining item here is the
  endianness bindings and related 8250 driver support.

   - DT endianness specification bindings

   - big-endian 8250 serial support

   - DT overlay unittest updates

   - various DT doc updates

   - compile fixes for OF_IRQ=n"

* tag 'devicetree-for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  frv: add io{read,write}{16,32}be functions
  mn10300: add io{read,write}{16,32}be functions
  Documentation: DT bindings: add doc for Altera's SoCFPGA platform
  of: base: improve of_get_next_child() kernel-doc
  Doc: dt: arch_timer: discourage clock-frequency use
  of: unittest: overlay: Keep track of created overlays
  of/fdt: fix allocation size for device node path
  serial: of_serial: Support big-endian register accesses
  serial: 8250: Add support for big-endian MMIO accesses
  of: Document {little,big,native}-endian bindings
  of/fdt: Add endianness helper function for early init code
  of: Add helper function to check MMIO register endianness
  of/fdt: Remove "reg" data prints from early_init_dt_scan_memory
  of: add vendor prefix for Artesyn
  of: Add dummy of_irq_to_resource_table() for IRQ_OF=n
  of: OF_IRQ should depend on IRQ_DOMAIN
parents 836ee487 04fca0e3

Documentation/devicetree/bindings/arm/altera.txt

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Altera's SoCFPGA platform device tree bindings

---------------------------------------------



Boards with Cyclone 5 SoC:

Required root node properties:

compatible = "altr,socfpga-cyclone5", "altr,socfpga";



Boards with Arria 5 SoC:

Required root node properties:

compatible = "altr,socfpga-arria5", "altr,socfpga";



Boards with Arria 10 SoC:

Required root node properties:

compatible = "altr,socfpga-arria10", "altr,socfpga";

Documentation/devicetree/bindings/arm/arch_timer.txt

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@@ -17,7 +17,10 @@ to deliver its interrupts via SPIs. 
- interrupts : Interrupt list for secure, non-secure, virtual and

  hypervisor timers, in that order.



- clock-frequency : The frequency of the main counter, in Hz. Optional.

- clock-frequency : The frequency of the main counter, in Hz. Should be present

  only where necessary to work around broken firmware which does not configure

  CNTFRQ on all CPUs to a uniform correct value. Use of this property is

  strongly discouraged; fix your firmware unless absolutely impossible.



- always-on : a boolean property. If present, the timer is powered through an

  always-on power domain, therefore it never loses context.
@@ -46,7 +49,8 @@ Example: 


- compatible : Should at least contain "arm,armv7-timer-mem".



- clock-frequency : The frequency of the main counter, in Hz. Optional.

- clock-frequency : The frequency of the main counter, in Hz. Should be present

  only when firmware has not configured the MMIO CNTFRQ registers.



- reg : The control frame base address.

Documentation/devicetree/bindings/common-properties.txt

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Common properties



The ePAPR specification does not define any properties related to hardware

byteswapping, but endianness issues show up frequently in porting Linux to

different machine types.  This document attempts to provide a consistent

way of handling byteswapping across drivers.



Optional properties:

 - big-endian: Boolean; force big endian register accesses

   unconditionally (e.g. ioread32be/iowrite32be).  Use this if you

   know the peripheral always needs to be accessed in BE mode.

 - little-endian: Boolean; force little endian register accesses

   unconditionally (e.g. readl/writel).  Use this if you know the

   peripheral always needs to be accessed in LE mode.

 - native-endian: Boolean; always use register accesses matched to the

   endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,

   BE vmlinux -> ioread32be/iowrite32be).  In this case no byteswaps

   will ever be performed.  Use this if the hardware "self-adjusts"

   register endianness based on the CPU's configured endianness.



If a binding supports these properties, then the binding should also

specify the default behavior if none of these properties are present.

In such cases, little-endian is the preferred default, but it is not

a requirement.  The of_device_is_big_endian() and of_fdt_is_big_endian()

helper functions do assume that little-endian is the default, because

most existing (PCI-based) drivers implicitly default to LE by using

readl/writel for MMIO accesses.



Examples:

Scenario 1 : CPU in LE mode & device in LE mode.

dev: dev@40031000 {

	      compatible = "name";

	      reg = <0x40031000 0x1000>;

	      ...

	      native-endian;

};



Scenario 2 : CPU in LE mode & device in BE mode.

dev: dev@40031000 {

	      compatible = "name";

	      reg = <0x40031000 0x1000>;

	      ...

	      big-endian;

};



Scenario 3 : CPU in BE mode & device in BE mode.

dev: dev@40031000 {

	      compatible = "name";

	      reg = <0x40031000 0x1000>;

	      ...

	      native-endian;

};



Scenario 4 : CPU in BE mode & device in LE mode.

dev: dev@40031000 {

	      compatible = "name";

	      reg = <0x40031000 0x1000>;

	      ...

	      little-endian;

};

Documentation/devicetree/bindings/vendor-prefixes.txt

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@@ -26,6 +26,7 @@ aptina Aptina Imaging 
arasan	Arasan Chip Systems

arm	ARM Ltd.

armadeus	ARMadeus Systems SARL

artesyn	Artesyn Embedded Technologies Inc.

asahi-kasei	Asahi Kasei Corp.

atmel	Atmel Corporation

auo	AU Optronics Corporation

arch/frv/include/asm/io.h

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@@ -342,6 +342,11 @@ static inline void iowrite32(u32 val, void __iomem *p) 
		__flush_PCI_writes();

}



#define ioread16be(addr)	be16_to_cpu(ioread16(addr))

#define ioread32be(addr)	be32_to_cpu(ioread32(addr))

#define iowrite16be(v, addr)	iowrite16(cpu_to_be16(v), (addr))

#define iowrite32be(v, addr)	iowrite32(cpu_to_be32(v), (addr))



static inline void ioread8_rep(void __iomem *p, void *dst, unsigned long count)

{

	io_insb((unsigned long) p, dst, count);

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