Commit d544e918 authored by Dhinakaran Pandiyan's avatar Dhinakaran Pandiyan Committed by Rodrigo Vivi
Browse files

drm/i915/psr: Remove open-coded PSR AUX transactions for SKL+ 



HSW and BDW have SRD_AUX_{CTL, STATUS} registers that the driver needs to
setup for the HW to use whenever exiting PSR. SKL+ hardware use hardcoded
values for the same and do not need any registers to be setup. So, use
drm_dp_dpcd_writeb() for a one-time write during PSR enable and setup the
PSR aux registers on HSW and BDW for later use by HW.

We also end up writing to reserved bits in SRD_AUX_CTL by reusing
intel_dp->get_aux_send_ctl() for HSW and BDW, fix this.

Since the AUX register setup is source side programming, move the call
to enable_source() from enable_sink().

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: default avatarJose Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180313034646.3721-2-dhinakaran.pandiyan@intel.com
parent b90eed08

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -3846,6 +3846,12 @@ enum { 
#define   EDP_PSR_IDLE_FRAME_SHIFT		0



#define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr_mmio_base + 0x10)

#define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		(3 << 26)

#define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	(0x1f << 20)

#define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	(0xf << 16)

#define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT	(1 << 11)

#define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK	(0x7ff)



#define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */



#define EDP_PSR_STATUS				_MMIO(dev_priv->psr_mmio_base + 0x40)

drivers/gpu/drm/i915/intel_psr.c

+22 −33
Original line number Diff line number Diff line
@@ -228,31 +228,12 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp) 
			   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);

}



static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,

				       enum port port)

{

	if (INTEL_GEN(dev_priv) >= 9)

		return DP_AUX_CH_CTL(port);

	else

		return EDP_PSR_AUX_CTL;

}



static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,

					enum port port, int index)

{

	if (INTEL_GEN(dev_priv) >= 9)

		return DP_AUX_CH_DATA(port, index);

	else

		return EDP_PSR_AUX_DATA(index);

}



static void hsw_psr_setup_aux(struct intel_dp *intel_dp)

{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_device *dev = dig_port->base.base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	uint32_t aux_clock_divider;

	i915_reg_t aux_ctl_reg;

	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);

	u32 aux_clock_divider, aux_ctl;

	int i;

	static const uint8_t aux_msg[] = {

		[0] = DP_AUX_NATIVE_WRITE << 4,

		[1] = DP_SET_POWER >> 8,
@@ -260,23 +241,25 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 
		[3] = 1 - 1,

		[4] = DP_SET_POWER_D0,

	};

	enum port port = dig_port->base.port;

	u32 aux_ctl;

	int i;

	u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |

			   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |

			   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |

			   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;



	BUILD_BUG_ON(sizeof(aux_msg) > 20);



	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);

	aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);



	/* Setup AUX registers */

	for (i = 0; i < sizeof(aux_msg); i += 4)

		I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),

		I915_WRITE(EDP_PSR_AUX_DATA(i >> 2),

			   intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));



	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);



	/* Start with bits set for DDI_AUX_CTL register */

	aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),

					     aux_clock_divider);

	I915_WRITE(aux_ctl_reg, aux_ctl);



	/* Select only valid bits for SRD_AUX_CTL */

	aux_ctl &= psr_aux_mask;

	I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl);

}



static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
@@ -303,7 +286,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) 
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,

				   DP_PSR_ENABLE);



	hsw_psr_setup_aux(intel_dp);

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);

}



static void vlv_psr_enable_source(struct intel_dp *intel_dp,
@@ -599,6 +582,12 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp, 


	psr_aux_io_power_get(intel_dp);



	/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+

	 * use hardcoded values PSR AUX transactions

	 */

	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

		hsw_psr_setup_aux(intel_dp);



	if (dev_priv->psr.psr2_support) {

		chicken = PSR2_VSC_ENABLE_PROG_HEADER;

		if (dev_priv->psr.y_cord_support)

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