Commit d53db442 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915: Move display device info capabilities to its own struct 



This helps separate what capabilities are display capabilities.

v3: Moving display struct right after flags (Lucas)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Suggested-by: default avatarJani Nikula <jani.nikula@linux.intel.com>
Suggested-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130232048.14216-2-jose.souza@intel.com
parent e1bf094b

drivers/gpu/drm/i915/i915_drv.h

+11 −11
Original line number Diff line number Diff line
@@ -2449,9 +2449,9 @@ intel_info(const struct drm_i915_private *dev_priv) 
	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \

})



#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.display.has_overlay)

#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \

		((dev_priv)->info.overlay_needs_physical)

		((dev_priv)->info.display.overlay_needs_physical)



/* Early gen2 have a totally busted CS tlb and require pinned batches. */

#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
@@ -2472,31 +2472,31 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \

					 !(IS_I915G(dev_priv) || \

					 IS_I915GM(dev_priv)))

#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)

#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)

#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.display.supports_tv)

#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.display.has_hotplug)



#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)

#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)

#define HAS_FBC(dev_priv)	((dev_priv)->info.display.has_fbc)

#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)



#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))



#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)

#define HAS_DP_MST(dev_priv)	((dev_priv)->info.display.has_dp_mst)



#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)

#define HAS_DDI(dev_priv)		 ((dev_priv)->info.display.has_ddi)

#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)

#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)

#define HAS_PSR(dev_priv)		 ((dev_priv)->info.display.has_psr)



#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)

#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)

#define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */



#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)

#define HAS_CSR(dev_priv)	((dev_priv)->info.display.has_csr)



#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)

#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)



#define HAS_IPC(dev_priv)		 ((dev_priv)->info.has_ipc)

#define HAS_IPC(dev_priv)		 ((dev_priv)->info.display.has_ipc)



/*

 * For now, anything with a GuC requires uCode loading, and then supports
@@ -2557,7 +2557,7 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)

#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)



#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)

#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.display.has_gmch_display)



#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)

drivers/gpu/drm/i915/i915_pci.c

+64 −53
Original line number Diff line number Diff line
@@ -79,8 +79,9 @@ 
#define GEN2_FEATURES \

	GEN(2), \

	.num_pipes = 1, \

	.has_overlay = 1, .overlay_needs_physical = 1, \

	.has_gmch_display = 1, \

	.display.has_overlay = 1, \

	.display.overlay_needs_physical = 1, \

	.display.has_gmch_display = 1, \

	.hws_needs_physical = 1, \

	.unfenced_needs_alignment = 1, \

	.ring_mask = RENDER_RING, \
@@ -93,7 +94,8 @@ 
static const struct intel_device_info intel_i830_info = {

	GEN2_FEATURES,

	PLATFORM(INTEL_I830),

	.is_mobile = 1, .cursor_needs_physical = 1,

	.is_mobile = 1,

	.display.cursor_needs_physical = 1,

	.num_pipes = 2, /* legal, last one wins */

};
@@ -107,8 +109,8 @@ static const struct intel_device_info intel_i85x_info = { 
	PLATFORM(INTEL_I85X),

	.is_mobile = 1,

	.num_pipes = 2, /* legal, last one wins */

	.cursor_needs_physical = 1,

	.has_fbc = 1,

	.display.cursor_needs_physical = 1,

	.display.has_fbc = 1,

};



static const struct intel_device_info intel_i865g_info = {
@@ -119,7 +121,7 @@ static const struct intel_device_info intel_i865g_info = { 
#define GEN3_FEATURES \

	GEN(3), \

	.num_pipes = 2, \

	.has_gmch_display = 1, \

	.display.has_gmch_display = 1, \

	.ring_mask = RENDER_RING, \

	.has_snoop = true, \

	.has_coherent_ggtt = true, \
@@ -131,8 +133,9 @@ static const struct intel_device_info intel_i915g_info = { 
	GEN3_FEATURES,

	PLATFORM(INTEL_I915G),

	.has_coherent_ggtt = false,

	.cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.display.cursor_needs_physical = 1,

	.display.has_overlay = 1,

	.display.overlay_needs_physical = 1,

	.hws_needs_physical = 1,

	.unfenced_needs_alignment = 1,

};
@@ -141,10 +144,11 @@ static const struct intel_device_info intel_i915gm_info = { 
	GEN3_FEATURES,

	PLATFORM(INTEL_I915GM),

	.is_mobile = 1,

	.cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.supports_tv = 1,

	.has_fbc = 1,

	.display.cursor_needs_physical = 1,

	.display.has_overlay = 1,

	.display.overlay_needs_physical = 1,

	.display.supports_tv = 1,

	.display.has_fbc = 1,

	.hws_needs_physical = 1,

	.unfenced_needs_alignment = 1,

};
@@ -152,8 +156,10 @@ static const struct intel_device_info intel_i915gm_info = { 
static const struct intel_device_info intel_i945g_info = {

	GEN3_FEATURES,

	PLATFORM(INTEL_I945G),

	.has_hotplug = 1, .cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.display.has_hotplug = 1,

	.display.cursor_needs_physical = 1,

	.display.has_overlay = 1,

	.display.overlay_needs_physical = 1,

	.hws_needs_physical = 1,

	.unfenced_needs_alignment = 1,

};
@@ -162,10 +168,12 @@ static const struct intel_device_info intel_i945gm_info = { 
	GEN3_FEATURES,

	PLATFORM(INTEL_I945GM),

	.is_mobile = 1,

	.has_hotplug = 1, .cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.supports_tv = 1,

	.has_fbc = 1,

	.display.has_hotplug = 1,

	.display.cursor_needs_physical = 1,

	.display.has_overlay = 1,

	.display.overlay_needs_physical = 1,

	.display.supports_tv = 1,

	.display.has_fbc = 1,

	.hws_needs_physical = 1,

	.unfenced_needs_alignment = 1,

};
@@ -173,23 +181,23 @@ static const struct intel_device_info intel_i945gm_info = { 
static const struct intel_device_info intel_g33_info = {

	GEN3_FEATURES,

	PLATFORM(INTEL_G33),

	.has_hotplug = 1,

	.has_overlay = 1,

	.display.has_hotplug = 1,

	.display.has_overlay = 1,

};



static const struct intel_device_info intel_pineview_info = {

	GEN3_FEATURES,

	PLATFORM(INTEL_PINEVIEW),

	.is_mobile = 1,

	.has_hotplug = 1,

	.has_overlay = 1,

	.display.has_hotplug = 1,

	.display.has_overlay = 1,

};



#define GEN4_FEATURES \

	GEN(4), \

	.num_pipes = 2, \

	.has_hotplug = 1, \

	.has_gmch_display = 1, \

	.display.has_hotplug = 1, \

	.display.has_gmch_display = 1, \

	.ring_mask = RENDER_RING, \

	.has_snoop = true, \

	.has_coherent_ggtt = true, \
@@ -200,7 +208,7 @@ static const struct intel_device_info intel_pineview_info = { 
static const struct intel_device_info intel_i965g_info = {

	GEN4_FEATURES,

	PLATFORM(INTEL_I965G),

	.has_overlay = 1,

	.display.has_overlay = 1,

	.hws_needs_physical = 1,

	.has_snoop = false,

};
@@ -208,9 +216,10 @@ static const struct intel_device_info intel_i965g_info = { 
static const struct intel_device_info intel_i965gm_info = {

	GEN4_FEATURES,

	PLATFORM(INTEL_I965GM),

	.is_mobile = 1, .has_fbc = 1,

	.has_overlay = 1,

	.supports_tv = 1,

	.is_mobile = 1,

	.display.has_fbc = 1,

	.display.has_overlay = 1,

	.display.supports_tv = 1,

	.hws_needs_physical = 1,

	.has_snoop = false,

};
@@ -224,15 +233,16 @@ static const struct intel_device_info intel_g45_info = { 
static const struct intel_device_info intel_gm45_info = {

	GEN4_FEATURES,

	PLATFORM(INTEL_GM45),

	.is_mobile = 1, .has_fbc = 1,

	.supports_tv = 1,

	.is_mobile = 1,

	.display.has_fbc = 1,

	.display.supports_tv = 1,

	.ring_mask = RENDER_RING | BSD_RING,

};



#define GEN5_FEATURES \

	GEN(5), \

	.num_pipes = 2, \

	.has_hotplug = 1, \

	.display.has_hotplug = 1, \

	.ring_mask = RENDER_RING | BSD_RING, \

	.has_snoop = true, \

	.has_coherent_ggtt = true, \
@@ -250,14 +260,15 @@ static const struct intel_device_info intel_ironlake_d_info = { 
static const struct intel_device_info intel_ironlake_m_info = {

	GEN5_FEATURES,

	PLATFORM(INTEL_IRONLAKE),

	.is_mobile = 1, .has_fbc = 1,

	.is_mobile = 1,

	.display.has_fbc = 1,

};



#define GEN6_FEATURES \

	GEN(6), \

	.num_pipes = 2, \

	.has_hotplug = 1, \

	.has_fbc = 1, \

	.display.has_hotplug = 1, \

	.display.has_fbc = 1, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \

	.has_coherent_ggtt = true, \

	.has_llc = 1, \
@@ -301,8 +312,8 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = { 
#define GEN7_FEATURES  \

	GEN(7), \

	.num_pipes = 3, \

	.has_hotplug = 1, \

	.has_fbc = 1, \

	.display.has_hotplug = 1, \

	.display.has_fbc = 1, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \

	.has_coherent_ggtt = true, \

	.has_llc = 1, \
@@ -359,8 +370,8 @@ static const struct intel_device_info intel_valleyview_info = { 
	.num_pipes = 2,

	.has_runtime_pm = 1,

	.has_rc6 = 1,

	.has_gmch_display = 1,

	.has_hotplug = 1,

	.display.has_gmch_display = 1,

	.display.has_hotplug = 1,

	.ppgtt = INTEL_PPGTT_FULL,

	.has_snoop = true,

	.has_coherent_ggtt = false,
@@ -374,10 +385,10 @@ static const struct intel_device_info intel_valleyview_info = { 
#define G75_FEATURES  \

	GEN7_FEATURES, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \

	.has_ddi = 1, \

	.display.has_ddi = 1, \

	.has_fpga_dbg = 1, \

	.has_psr = 1, \

	.has_dp_mst = 1, \

	.display.has_psr = 1, \

	.display.has_dp_mst = 1, \

	.has_rc6p = 0 /* RC6p removed-by HSW */, \

	.has_runtime_pm = 1
@@ -444,14 +455,14 @@ static const struct intel_device_info intel_cherryview_info = { 
	PLATFORM(INTEL_CHERRYVIEW),

	GEN(8),

	.num_pipes = 3,

	.has_hotplug = 1,

	.display.has_hotplug = 1,

	.is_lp = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	.has_64bit_reloc = 1,

	.has_runtime_pm = 1,

	.has_rc6 = 1,

	.has_logical_ring_contexts = 1,

	.has_gmch_display = 1,

	.display.has_gmch_display = 1,

	.ppgtt = INTEL_PPGTT_FULL,

	.has_reset_engine = 1,

	.has_snoop = true,
@@ -473,15 +484,15 @@ static const struct intel_device_info intel_cherryview_info = { 
	GEN(9), \

	GEN9_DEFAULT_PAGE_SIZES, \

	.has_logical_ring_preemption = 1, \

	.has_csr = 1, \

	.display.has_csr = 1, \

	.has_guc = 1, \

	.has_ipc = 1, \

	.display.has_ipc = 1, \

	.ddb_size = 896



#define SKL_PLATFORM \

	GEN9_FEATURES, \

	/* Display WA #0477 WaDisableIPC: skl */ \

	.has_ipc = 0, \

	.display.has_ipc = 0, \

	PLATFORM(INTEL_SKYLAKE)



static const struct intel_device_info intel_skylake_gt1_info = {
@@ -512,19 +523,19 @@ static const struct intel_device_info intel_skylake_gt4_info = { 
#define GEN9_LP_FEATURES \

	GEN(9), \

	.is_lp = 1, \

	.has_hotplug = 1, \

	.display.has_hotplug = 1, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \

	.num_pipes = 3, \

	.has_64bit_reloc = 1, \

	.has_ddi = 1, \

	.display.has_ddi = 1, \

	.has_fpga_dbg = 1, \

	.has_fbc = 1, \

	.has_psr = 1, \

	.display.has_fbc = 1, \

	.display.has_psr = 1, \

	.has_runtime_pm = 1, \

	.has_pooled_eu = 0, \

	.has_csr = 1, \

	.display.has_csr = 1, \

	.has_rc6 = 1, \

	.has_dp_mst = 1, \

	.display.has_dp_mst = 1, \

	.has_logical_ring_contexts = 1, \

	.has_logical_ring_preemption = 1, \

	.has_guc = 1, \
@@ -532,7 +543,7 @@ static const struct intel_device_info intel_skylake_gt4_info = { 
	.has_reset_engine = 1, \

	.has_snoop = true, \

	.has_coherent_ggtt = false, \

	.has_ipc = 1, \

	.display.has_ipc = 1, \

	GEN9_DEFAULT_PAGE_SIZES, \

	GEN_DEFAULT_PIPEOFFSETS, \

	IVB_CURSOR_OFFSETS, \

drivers/gpu/drm/i915/intel_device_info.c

+4 −0
Original line number Diff line number Diff line
@@ -77,6 +77,10 @@ void intel_device_info_dump_flags(const struct intel_device_info *info, 
#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));

	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);

#undef PRINT_FLAG



#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));

	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);

#undef PRINT_FLAG

}



static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)

drivers/gpu/drm/i915/intel_device_info.h

+21 −11
Original line number Diff line number Diff line
@@ -89,35 +89,38 @@ enum intel_ppgtt { 
	func(is_alpha_support); \

	/* Keep has_* in alphabetical order */ \

	func(has_64bit_reloc); \

	func(has_csr); \

	func(has_ddi); \

	func(has_dp_mst); \

	func(has_reset_engine); \

	func(has_fbc); \

	func(has_fpga_dbg); \

	func(has_gmch_display); \

	func(has_guc); \

	func(has_guc_ct); \

	func(has_hotplug); \

	func(has_l3_dpf); \

	func(has_llc); \

	func(has_logical_ring_contexts); \

	func(has_logical_ring_elsq); \

	func(has_logical_ring_preemption); \

	func(has_overlay); \

	func(has_pooled_eu); \

	func(has_psr); \

	func(has_rc6); \

	func(has_rc6p); \

	func(has_runtime_pm); \

	func(has_snoop); \

	func(has_coherent_ggtt); \

	func(unfenced_needs_alignment); \

	func(hws_needs_physical);



#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \

	/* Keep in alphabetical order */ \

	func(cursor_needs_physical); \

	func(hws_needs_physical); \

	func(has_csr); \

	func(has_ddi); \

	func(has_dp_mst); \

	func(has_fbc); \

	func(has_gmch_display); \

	func(has_hotplug); \

	func(has_ipc); \

	func(has_overlay); \

	func(has_psr); \

	func(overlay_needs_physical); \

	func(supports_tv); \

	func(has_ipc);

	func(supports_tv);



#define GEN_MAX_SLICES		(6) /* CNL upper bound */

#define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */
@@ -172,6 +175,13 @@ struct intel_device_info { 
#define DEFINE_FLAG(name) u8 name:1

	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);

#undef DEFINE_FLAG



	struct {

#define DEFINE_FLAG(name) u8 name:1

		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);

#undef DEFINE_FLAG

	} display;



	u16 ddb_size; /* in blocks */



	/* Register offsets for the various display pipes and transcoders */

drivers/gpu/drm/i915/intel_display.c

+2 −2
Original line number Diff line number Diff line
@@ -9717,7 +9717,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state) 
	const struct drm_i915_gem_object *obj = intel_fb_obj(fb);

	u32 base;



	if (INTEL_INFO(dev_priv)->cursor_needs_physical)

	if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)

		base = obj->phys_handle->busaddr;

	else

		base = intel_plane_ggtt_offset(plane_state);
@@ -13303,7 +13303,7 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state) 
	struct i915_vma *vma;



	if (plane->id == PLANE_CURSOR &&

	    INTEL_INFO(dev_priv)->cursor_needs_physical) {

	    INTEL_INFO(dev_priv)->display.cursor_needs_physical) {

		struct drm_i915_gem_object *obj = intel_fb_obj(fb);

		const int align = intel_cursor_alignment(dev_priv);

		int err;

CRA Git | Maintained and supported by SUSTech CRA and CCSE