Commit d532f3d2 authored by Steven J. Hill's avatar Steven J. Hill Committed by Ralf Baechle
Browse files

MIPS: Allow ASID size to be determined at boot time. 

Original patch by Ralf Baechle and removed by Harold Koerfgen
with commit f67e4ffc79905482c3b9b8c8dd65197bac7eb508. This
allows for more generic kernels since the size of the ASID
and corresponding masks can be determined at run-time. This
patch is also required for the new Aptiv cores and has been
tested on Malta and Malta Aptiv platforms.

[ralf@linux-mips.org: Added relevant part of fix
https://patchwork.linux-mips.org/patch/5213/

]

Signed-off-by: default avatarSteven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 49bffbdc

arch/mips/include/asm/mmu_context.h

+59 −36
Original line number Diff line number Diff line
@@ -62,45 +62,68 @@ extern unsigned long pgd_current[]; 
	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)

#endif

#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/

#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)



#define ASID_INC	0x40

#define ASID_MASK	0xfc0



#elif defined(CONFIG_CPU_R8000)



#define ASID_INC	0x10

#define ASID_MASK	0xff0



#elif defined(CONFIG_MIPS_MT_SMTC)



#define ASID_INC	0x1

extern unsigned long smtc_asid_mask;

#define ASID_MASK	(smtc_asid_mask)

#define HW_ASID_MASK	0xff

/* End SMTC/34K debug hack */

#else /* FIXME: not correct for R6000 */



#define ASID_INC	0x1

#define ASID_MASK	0xff

#define ASID_INC(asid)						\

({								\

	unsigned long __asid = asid;				\

	__asm__("1:\taddiu\t%0,1\t\t\t\t# patched\n\t"		\

	".section\t__asid_inc,\"a\"\n\t"			\

	".word\t1b\n\t"						\

	".previous"						\

	:"=r" (__asid)						\

	:"0" (__asid));						\

	__asid;							\

})

#define ASID_MASK(asid)						\

({								\

	unsigned long __asid = asid;				\

	__asm__("1:\tandi\t%0,%1,0xfc0\t\t\t# patched\n\t"	\

	".section\t__asid_mask,\"a\"\n\t"			\

	".word\t1b\n\t"						\

	".previous"						\

	:"=r" (__asid)						\

	:"r" (__asid));						\

	__asid;							\

})

#define ASID_VERSION_MASK					\

({								\

	unsigned long __asid;					\

	__asm__("1:\taddiu\t%0,$0,0xff00\t\t\t\t# patched\n\t"	\

	".section\t__asid_version_mask,\"a\"\n\t"		\

	".word\t1b\n\t"						\

	".previous"						\

	:"=r" (__asid));					\

	__asid;							\

})

#define ASID_FIRST_VERSION					\

({								\

	unsigned long __asid = asid;				\

	__asm__("1:\tli\t%0,0x100\t\t\t\t# patched\n\t"		\

	".section\t__asid_first_version,\"a\"\n\t"		\

	".word\t1b\n\t"						\

	".previous"						\

	:"=r" (__asid));					\

	__asid;							\

})



#define ASID_FIRST_VERSION_R3000	0x1000

#define ASID_FIRST_VERSION_R4000	0x100

#define ASID_FIRST_VERSION_R8000	0x1000

#define ASID_FIRST_VERSION_RM9000	0x1000



#ifdef CONFIG_MIPS_MT_SMTC

#define SMTC_HW_ASID_MASK		0xff

extern unsigned int smtc_asid_mask;

#endif



#define cpu_context(cpu, mm)	((mm)->context.asid[cpu])

#define cpu_asid(cpu, mm)	(cpu_context((cpu), (mm)) & ASID_MASK)

#define cpu_asid(cpu, mm)	ASID_MASK(cpu_context((cpu), (mm)))

#define asid_cache(cpu)		(cpu_data[cpu].asid_cache)



static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)

{

}



/*

 *  All unused by hardware upper bits will be considered

 *  as a software asid extension.

 */

#define ASID_VERSION_MASK  ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))

#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)



#ifndef CONFIG_MIPS_MT_SMTC

/* Normal, classic MIPS get_new_mmu_context */

static inline void
@@ -108,7 +131,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 
{

	unsigned long asid = asid_cache(cpu);



	if (! ((asid += ASID_INC) & ASID_MASK) ) {

	if (!ASID_MASK((asid = ASID_INC(asid)))) {

		if (cpu_has_vtag_icache)

			flush_icache_all();

		local_flush_tlb_all();	/* start new asid cycle */
@@ -166,7 +189,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 
	 * free up the ASID value for use and flush any old

	 * instances of it from the TLB.

	 */

	oldasid = (read_c0_entryhi() & ASID_MASK);

	oldasid = ASID_MASK(read_c0_entryhi());

	if(smtc_live_asid[mytlb][oldasid]) {

		smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);

		if(smtc_live_asid[mytlb][oldasid] == 0)
@@ -177,7 +200,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 
	 * having ASID_MASK smaller than the hardware maximum,

	 * make sure no "soft" bits become "hard"...

	 */

	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |

	write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) |

			 cpu_asid(cpu, next));

	ehb(); /* Make sure it propagates to TCStatus */

	evpe(mtflags);
@@ -230,14 +253,14 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) 
#ifdef CONFIG_MIPS_MT_SMTC

	/* See comments for similar code above */

	mtflags = dvpe();

	oldasid = read_c0_entryhi() & ASID_MASK;

	oldasid = ASID_MASK(read_c0_entryhi());

	if(smtc_live_asid[mytlb][oldasid]) {

		smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);

		if(smtc_live_asid[mytlb][oldasid] == 0)

			 smtc_flush_tlb_asid(oldasid);

	}

	/* See comments for similar code above */

	write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |

	write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) |

	                 cpu_asid(cpu, next));

	ehb(); /* Make sure it propagates to TCStatus */

	evpe(mtflags);
@@ -275,14 +298,14 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu) 
#ifdef CONFIG_MIPS_MT_SMTC

		/* See comments for similar code above */

		prevvpe = dvpe();

		oldasid = (read_c0_entryhi() & ASID_MASK);

		oldasid = ASID_MASK(read_c0_entryhi());

		if (smtc_live_asid[mytlb][oldasid]) {

			smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);

			if(smtc_live_asid[mytlb][oldasid] == 0)

				smtc_flush_tlb_asid(oldasid);

		}

		/* See comments for similar code above */

		write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)

		write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK)

				| cpu_asid(cpu, mm));

		ehb(); /* Make sure it propagates to TCStatus */

		evpe(prevvpe);

arch/mips/kernel/genex.S

+1 −1
Original line number Diff line number Diff line
@@ -480,7 +480,7 @@ NESTED(nmi_handler, PT_SIZE, sp) 
	.set	noreorder

	/* check if TLB contains a entry for EPC */

	MFC0	k1, CP0_ENTRYHI

	andi	k1, 0xff	/* ASID_MASK */

	andi	k1, 0xff	/* ASID_MASK patched at run-time!! */

	MFC0	k0, CP0_EPC

	PTR_SRL k0, _PAGE_SHIFT + 1

	PTR_SLL k0, _PAGE_SHIFT + 1

arch/mips/kernel/smtc.c

+5 −5
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ static int vpe0limit; 
static int ipibuffers;

static int nostlb;

static int asidmask;

unsigned long smtc_asid_mask = 0xff;

unsigned int smtc_asid_mask = 0xff;



static int __init vpe0tcs(char *str)

{
@@ -1395,7 +1395,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 
	asid = asid_cache(cpu);



	do {

		if (!((asid += ASID_INC) & ASID_MASK) ) {

		if (!ASID_MASK(ASID_INC(asid))) {

			if (cpu_has_vtag_icache)

				flush_icache_all();

			/* Traverse all online CPUs (hack requires contiguous range) */
@@ -1414,7 +1414,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 
						mips_ihb();

					}

					tcstat = read_tc_c0_tcstatus();

					smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i);

					smtc_live_asid[tlb][ASID_MASK(tcstat)] |= (asiduse)(0x1 << i);

					if (!prevhalt)

						write_tc_c0_tchalt(0);

				}
@@ -1423,7 +1423,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 
				asid = ASID_FIRST_VERSION;

			local_flush_tlb_all();	/* start new asid cycle */

		}

	} while (smtc_live_asid[tlb][(asid & ASID_MASK)]);

	} while (smtc_live_asid[tlb][ASID_MASK(asid)]);



	/*

	 * SMTC shares the TLB within VPEs and possibly across all VPEs.
@@ -1461,7 +1461,7 @@ void smtc_flush_tlb_asid(unsigned long asid) 
		tlb_read();

		ehb();

		ehi = read_c0_entryhi();

		if ((ehi & ASID_MASK) == asid) {

		if (ASID_MASK(ehi) == asid) {

		    /*

		     * Invalidate only entries with specified ASID,

		     * makiing sure all entries differ.

arch/mips/kernel/traps.c

+4 −2
Original line number Diff line number Diff line
@@ -1547,6 +1547,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) 
	unsigned int cpu = smp_processor_id();

	unsigned int status_set = ST0_CU0;

	unsigned int hwrena = cpu_hwrena_impl_bits;

	unsigned long asid = 0;

#ifdef CONFIG_MIPS_MT_SMTC

	int secondaryTC = 0;

	int bootTC = (cpu == 0);
@@ -1630,8 +1631,9 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) 
	}

#endif /* CONFIG_MIPS_MT_SMTC */



	if (!cpu_data[cpu].asid_cache)

		cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;

	asid = ASID_FIRST_VERSION;

	cpu_data[cpu].asid_cache = asid;

	TLBMISS_HANDLER_SETUP();



	atomic_inc(&init_mm.mm_count);

	current->active_mm = &init_mm;

arch/mips/lib/dump_tlb.c

+3 −2
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <asm/page.h>

#include <asm/pgtable.h>

#include <asm/tlbdebug.h>

#include <asm/mmu_context.h>



static inline const char *msk2str(unsigned int mask)

{
@@ -55,7 +56,7 @@ static void dump_tlb(int first, int last) 
	s_pagemask = read_c0_pagemask();

	s_entryhi = read_c0_entryhi();

	s_index = read_c0_index();

	asid = s_entryhi & 0xff;

	asid = ASID_MASK(s_entryhi);



	for (i = first; i <= last; i++) {

		write_c0_index(i);
@@ -85,7 +86,7 @@ static void dump_tlb(int first, int last) 


			printk("va=%0*lx asid=%02lx\n",

			       width, (entryhi & ~0x1fffUL),

			       entryhi & 0xff);

			       ASID_MASK(entryhi));

			printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",

			       width,

			       (entrylo0 << 6) & PAGE_MASK, c0,

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