Commit d51d0af4 authored by Marc Zyngier's avatar Marc Zyngier Committed by Jason Cooper
Browse files

irqchip: gic: Move some bits of GICv2 to a library-type file 



A few GICv2 low-level function are actually very useful to GICv3,
and it makes some sense to share them across the two drivers.
They end-up in their own file, with an additional parameter used
to ensure an optional synchronization (unused on GICv2).

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1404140510-5382-2-git-send-email-marc.zyngier@arm.com


Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 7171511e

drivers/irqchip/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o 
obj-$(CONFIG_ARCH_SUNXI)		+= irq-sun4i.o

obj-$(CONFIG_ARCH_SUNXI)		+= irq-sunxi-nmi.o

obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o

obj-$(CONFIG_ARM_GIC)			+= irq-gic.o

obj-$(CONFIG_ARM_GIC)			+= irq-gic.o irq-gic-common.o

obj-$(CONFIG_ARM_NVIC)			+= irq-nvic.o

obj-$(CONFIG_ARM_VIC)			+= irq-vic.o

obj-$(CONFIG_IMGPDC_IRQ)		+= irq-imgpdc.o

drivers/irqchip/irq-gic-common.c

0 → 100644
+115 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2002 ARM Limited, All Rights Reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/irq.h>

#include <linux/irqchip/arm-gic.h>



#include "irq-gic-common.h"



void gic_configure_irq(unsigned int irq, unsigned int type,

		       void __iomem *base, void (*sync_access)(void))

{

	u32 enablemask = 1 << (irq % 32);

	u32 enableoff = (irq / 32) * 4;

	u32 confmask = 0x2 << ((irq % 16) * 2);

	u32 confoff = (irq / 16) * 4;

	bool enabled = false;

	u32 val;



	/*

	 * Read current configuration register, and insert the config

	 * for "irq", depending on "type".

	 */

	val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);

	if (type == IRQ_TYPE_LEVEL_HIGH)

		val &= ~confmask;

	else if (type == IRQ_TYPE_EDGE_RISING)

		val |= confmask;



	/*

	 * As recommended by the spec, disable the interrupt before changing

	 * the configuration

	 */

	if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {

		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);

		if (sync_access)

			sync_access();

		enabled = true;

	}



	/*

	 * Write back the new configuration, and possibly re-enable

	 * the interrupt.

	 */

	writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);



	if (enabled)

		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);



	if (sync_access)

		sync_access();

}



void __init gic_dist_config(void __iomem *base, int gic_irqs,

			    void (*sync_access)(void))

{

	unsigned int i;



	/*

	 * Set all global interrupts to be level triggered, active low.

	 */

	for (i = 32; i < gic_irqs; i += 16)

		writel_relaxed(0, base + GIC_DIST_CONFIG + i / 4);



	/*

	 * Set priority on all global interrupts.

	 */

	for (i = 32; i < gic_irqs; i += 4)

		writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i);



	/*

	 * Disable all interrupts.  Leave the PPI and SGIs alone

	 * as they are enabled by redistributor registers.

	 */

	for (i = 32; i < gic_irqs; i += 32)

		writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i / 8);



	if (sync_access)

		sync_access();

}



void gic_cpu_config(void __iomem *base, void (*sync_access)(void))

{

	int i;



	/*

	 * Deal with the banked PPI and SGI interrupts - disable all

	 * PPI interrupts, ensure all SGI interrupts are enabled.

	 */

	writel_relaxed(0xffff0000, base + GIC_DIST_ENABLE_CLEAR);

	writel_relaxed(0x0000ffff, base + GIC_DIST_ENABLE_SET);



	/*

	 * Set priority on PPI and SGI interrupts

	 */

	for (i = 0; i < 32; i += 4)

		writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);



	if (sync_access)

		sync_access();

}

drivers/irqchip/irq-gic-common.h

0 → 100644
+29 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2002 ARM Limited, All Rights Reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#ifndef _IRQ_GIC_COMMON_H

#define _IRQ_GIC_COMMON_H



#include <linux/of.h>

#include <linux/irqdomain.h>



void gic_configure_irq(unsigned int irq, unsigned int type,

                       void __iomem *base, void (*sync_access)(void));

void gic_dist_config(void __iomem *base, int gic_irqs,

		     void (*sync_access)(void));

void gic_cpu_config(void __iomem *base, void (*sync_access)(void));



#endif /* _IRQ_GIC_COMMON_H */

drivers/irqchip/irq-gic.c

+4 −55
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
#include <asm/exception.h>

#include <asm/smp_plat.h>



#include "irq-gic-common.h"

#include "irqchip.h"



union gic_base {
@@ -188,12 +189,6 @@ static int gic_set_type(struct irq_data *d, unsigned int type) 
{

	void __iomem *base = gic_dist_base(d);

	unsigned int gicirq = gic_irq(d);

	u32 enablemask = 1 << (gicirq % 32);

	u32 enableoff = (gicirq / 32) * 4;

	u32 confmask = 0x2 << ((gicirq % 16) * 2);

	u32 confoff = (gicirq / 16) * 4;

	bool enabled = false;

	u32 val;



	/* Interrupt configuration for SGIs can't be changed */

	if (gicirq < 16)
@@ -207,25 +202,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) 
	if (gic_arch_extn.irq_set_type)

		gic_arch_extn.irq_set_type(d, type);



	val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);

	if (type == IRQ_TYPE_LEVEL_HIGH)

		val &= ~confmask;

	else if (type == IRQ_TYPE_EDGE_RISING)

		val |= confmask;



	/*

	 * As recommended by the spec, disable the interrupt before changing

	 * the configuration

	 */

	if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {

		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);

		enabled = true;

	}



	writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);



	if (enabled)

		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);

	gic_configure_irq(gicirq, type, base, NULL);



	raw_spin_unlock(&irq_controller_lock);
@@ -386,12 +363,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic) 


	writel_relaxed(0, base + GIC_DIST_CTRL);



	/*

	 * Set all global interrupts to be level triggered, active low.

	 */

	for (i = 32; i < gic_irqs; i += 16)

		writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);



	/*

	 * Set all global interrupts to this CPU only.

	 */
@@ -401,18 +372,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic) 
	for (i = 32; i < gic_irqs; i += 4)

		writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);



	/*

	 * Set priority on all global interrupts.

	 */

	for (i = 32; i < gic_irqs; i += 4)

		writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);



	/*

	 * Disable all interrupts.  Leave the PPI and SGIs alone

	 * as these enables are banked registers.

	 */

	for (i = 32; i < gic_irqs; i += 32)

		writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);

	gic_dist_config(base, gic_irqs, NULL);



	writel_relaxed(1, base + GIC_DIST_CTRL);

}
@@ -439,18 +399,7 @@ static void gic_cpu_init(struct gic_chip_data *gic) 
		if (i != cpu)

			gic_cpu_map[i] &= ~cpu_mask;



	/*

	 * Deal with the banked PPI and SGI interrupts - disable all

	 * PPI interrupts, ensure all SGI interrupts are enabled.

	 */

	writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);

	writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);



	/*

	 * Set priority on PPI and SGI interrupts

	 */

	for (i = 0; i < 32; i += 4)

		writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);

	gic_cpu_config(dist_base, NULL);



	writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);

	writel_relaxed(1, base + GIC_CPU_CTRL);

CRA Git | Maintained and supported by SUSTech CRA and CCSE