Commit d50a8b48 authored by Bhupesh Sharma's avatar Bhupesh Sharma Committed by Arnd Bergmann
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dts/ls2080a: Update DTSI to add support of SP805 WDT 



This patch updates the LS2080a DTSI (DTS Include) file to add
support for eight SP805 Watchdog units which can be used to
reset the eight Cortex-A57 cores available on LS2080A.

Signed-off-by: default avatarBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 766faef1

arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

+56 −0
Original line number Diff line number Diff line
@@ -205,6 +205,62 @@ 
			interrupts = <0 32 0x4>; /* Level high type */

		};



		cluster1_core0_watchdog: wdt@c000000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc000000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

		};



		cluster1_core1_watchdog: wdt@c010000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc010000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

		};



		cluster2_core0_watchdog: wdt@c100000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc100000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

		};



		cluster2_core1_watchdog: wdt@c110000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc110000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

		};



		cluster3_core0_watchdog: wdt@c200000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc200000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

		};



		cluster3_core1_watchdog: wdt@c210000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc210000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

		};



		cluster4_core0_watchdog: wdt@c300000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc300000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

		};



		cluster4_core1_watchdog: wdt@c310000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc310000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clock-names = "apb_pclk", "wdog_clk";

		};



		fsl_mc: fsl-mc@80c000000 {

			compatible = "fsl,qoriq-mc";

			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */

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