Merge tag 'for_3.17' of...

Berlin SATA PHY

---------------

Required properties:

- compatible: should be "marvell,berlin2q-sata-phy"

- address-cells: should be 1

- size-cells: should be 0

- phy-cells: from the generic PHY bindings, must be 1

- reg: address and length of the register

- clocks: reference to the clock entry

Sub-nodes:

Each PHY should be represented as a sub-node.

Sub-nodes required properties:

- reg: the PHY number

Example:

	sata_phy: phy@f7e900a0 {

		compatible = "marvell,berlin2q-sata-phy";

		reg = <0xf7e900a0 0x200>;

		clocks = <&chip CLKID_SATA>;

		#address-cells = <1>;

		#size-cells = <0>;

		#phy-cells = <1>;

		sata-phy@0 {

			reg = <0>;

		};

		sata-phy@1 {

			reg = <1>;

		};

	};

Hisilicon hix5hd2 SATA PHY

-----------------------

Required properties:

- compatible: should be "hisilicon,hix5hd2-sata-phy"

- reg: offset and length of the PHY registers

- #phy-cells: must be 0

Refer to phy/phy-bindings.txt for the generic PHY binding properties

Optional Properties:

- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.

- hisilicon,power-reg: offset and bit number within peripheral-syscon,

	register of controlling sata power supply.

Example:

	sata_phy: phy@f9900000 {

		compatible = "hisilicon,hix5hd2-sata-phy";

		reg = <0xf9900000 0x10000>;

		#phy-cells = <0>;

		hisilicon,peripheral-syscon = <&peripheral_ctrl>;

		hisilicon,power-reg = <0x8 10>;

	};

		provider can use the values in cells to find the appropriate

		PHY.

Optional Properties:

phy-supply:	Phandle to a regulator that provides power to the PHY. This

		regulator will be managed during the PHY power on/off sequence.

For example:

phys: phy {

STMicroelectronics STi MIPHY365x PHY binding

============================================

This binding describes a miphy device that is used to control PHY hardware

for SATA and PCIe.

Required properties (controller (parent) node):

- compatible    : Should be "st,miphy365x-phy"

- st,syscfg     : Should be a phandle of the system configuration register group

		  which contain the SATA, PCIe mode setting bits

Required nodes	:  A sub-node is required for each channel the controller

		   provides. Address range information including the usual

		   'reg' and 'reg-names' properties are used inside these

		   nodes to describe the controller's topology. These nodes

		   are translated by the driver's .xlate() function.

Required properties (port (child) node):

- #phy-cells 	: Should be 1 (See second example)

		  Cell after port phandle is device type from:

			- MIPHY_TYPE_SATA

			- MIPHY_TYPE_PCI

- reg        	: Address and length of register sets for each device in

		  "reg-names"

- reg-names     : The names of the register addresses corresponding to the

		  registers filled in "reg":

			- sata:   For SATA devices

			- pcie:   For PCIe devices

			- syscfg: To specify the syscfg based config register

Optional properties (port (child) node):

- st,sata-gen	     :	Generation of locally attached SATA IP. Expected values

			are {1,2,3). If not supplied generation 1 hardware will

			be expected

- st,pcie-tx-pol-inv :	Bool property to invert the polarity PCIe Tx (Txn/Txp)

- st,sata-tx-pol-inv :	Bool property to invert the polarity SATA Tx (Txn/Txp)

Example:

	miphy365x_phy: miphy365x@fe382000 {

		compatible      = "st,miphy365x-phy";

		st,syscfg  	= <&syscfg_rear>;

		#address-cells	= <1>;

		#size-cells	= <1>;

		ranges;

		phy_port0: port@fe382000 {

			reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;

			reg-names = "sata", "pcie", "syscfg";

			#phy-cells = <1>;

			st,sata-gen = <3>;

		};

		phy_port1: port@fe38a000 {

			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;

			reg-names = "sata", "pcie", "syscfg";

			#phy-cells = <1>;

			st,pcie-tx-pol-inv;

		};

	};

Specifying phy control of devices

=================================

Device nodes should specify the configuration required in their "phys"

property, containing a phandle to the phy port node and a device type.

Example:

#include <dt-bindings/phy/phy-miphy365x.h>

	sata0: sata@fe380000 {

		...

		phys	  = <&phy_port0 MIPHY_TYPE_SATA>;

		...

	};

Qualcomm APQ8064 SATA PHY Controller

------------------------------------

SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.

Each SATA PHY controller should have its own node.

Required properties:

- compatible: compatible list, contains "qcom,apq8064-sata-phy".

- reg: offset and length of the SATA PHY register set;

- #phy-cells: must be zero

- clocks: a list of phandles and clock-specifier pairs, one for each entry in

  clock-names.

- clock-names: must be "cfg" for phy config clock.

Example:

	sata_phy: sata-phy@1b400000 {

		compatible = "qcom,apq8064-sata-phy";

		reg = <0x1b400000 0x200>;

		clocks = <&gcc SATA_PHY_CFG_CLK>;

		clock-names = "cfg";

		#phy-cells = <0>;

	};