Commit d50240a5 authored by Will Deacon's avatar Will Deacon Committed by Catalin Marinas
Browse files

arm64: mm: permit use of tagged pointers at EL0 



TCR.TBI0 can be used to cause hardware address translation to ignore the
top byte of userspace virtual addresses. Whilst not especially useful in
standard C programs, this can be used by JITs to `tag' pointers with
various pieces of metadata.

This patch enables this bit for AArch64 Linux, and adds a new file to
Documentation/arm64/ which describes some potential caveats when using
tagged virtual addresses.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 909e3ee4

Documentation/arm64/tagged-pointers.txt

0 → 100644
+34 −0
Original line number Diff line number Diff line 
		Tagged virtual addresses in AArch64 Linux

		=========================================



Author: Will Deacon <will.deacon@arm.com>

Date  : 12 June 2013



This document briefly describes the provision of tagged virtual

addresses in the AArch64 translation system and their potential uses

in AArch64 Linux.



The kernel configures the translation tables so that translations made

via TTBR0 (i.e. userspace mappings) have the top byte (bits 63:56) of

the virtual address ignored by the translation hardware. This frees up

this byte for application use, with the following caveats:



	(1) The kernel requires that all user addresses passed to EL1

	    are tagged with tag 0x00. This means that any syscall

	    parameters containing user virtual addresses *must* have

	    their top byte cleared before trapping to the kernel.



	(2) Tags are not guaranteed to be preserved when delivering

	    signals. This means that signal handlers in applications

	    making use of tags cannot rely on the tag information for

	    user virtual addresses being maintained for fields inside

	    siginfo_t. One exception to this rule is for signals raised

	    in response to debug exceptions, where the tag information

	    will be preserved.



	(3) Special care should be taken when using tagged pointers,

	    since it is likely that C compilers will not hazard two

	    addresses differing only in the upper bits.



The architecture prevents the use of a tagged PC, so the upper byte will

be set to a sign-extension of bit 55 on exception return.

arch/arm64/include/asm/pgtable-hwdef.h

+1 −0
Original line number Diff line number Diff line
@@ -122,5 +122,6 @@ 
#define TCR_TG1_64K		(UL(1) << 30)

#define TCR_IPS_40BIT		(UL(2) << 32)

#define TCR_ASID16		(UL(1) << 36)

#define TCR_TBI0		(UL(1) << 37)



#endif

arch/arm64/kernel/entry.S

+1 −0
Original line number Diff line number Diff line
@@ -423,6 +423,7 @@ el0_da: 
	 * Data abort handling

	 */

	mrs	x0, far_el1

	bic	x0, x0, #(0xff << 56)

	disable_step x1

	isb

	enable_dbg

arch/arm64/mm/proc.S

+1 −1
Original line number Diff line number Diff line
@@ -147,7 +147,7 @@ ENTRY(__cpu_setup) 
	 * both user and kernel.

	 */

	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \

		      TCR_ASID16 | (1 << 31)

		      TCR_ASID16 | TCR_TBI0 | (1 << 31)

#ifdef CONFIG_ARM64_64K_PAGES

	orr	x10, x10, TCR_TG0_64K

	orr	x10, x10, TCR_TG1_64K

CRA Git | Maintained and supported by SUSTech CRA and CCSE