Commit d4e17687 authored by Yangbo Lu's avatar Yangbo Lu Committed by David S. Miller
Browse files

ptp_qoriq: fix register memory map 



The 1588 timer on eTSEC Ethernet controller uses different
register memory map with DPAA Ethernet controller.
Now the new ENETC Ethernet controller uses same reigster
memory map with DPAA. To support ENETC, let's use register
memory map of DPAA/ENETC in default.

Signed-off-by: default avatarYangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2843bf51

drivers/ptp/ptp_qoriq.c

+6 −5
Original line number Diff line number Diff line
@@ -504,11 +504,12 @@ int ptp_qoriq_init(struct ptp_qoriq *ptp_qoriq, void __iomem *base, 
		ptp_qoriq->write = qoriq_write_be;

	}



	if (of_device_is_compatible(node, "fsl,fman-ptp-timer")) {

		ptp_qoriq->regs.ctrl_regs = base + FMAN_CTRL_REGS_OFFSET;

		ptp_qoriq->regs.alarm_regs = base + FMAN_ALARM_REGS_OFFSET;

		ptp_qoriq->regs.fiper_regs = base + FMAN_FIPER_REGS_OFFSET;

		ptp_qoriq->regs.etts_regs = base + FMAN_ETTS_REGS_OFFSET;

	/* The eTSEC uses differnt memory map with DPAA/ENETC */

	if (of_device_is_compatible(node, "fsl,etsec-ptp")) {

		ptp_qoriq->regs.ctrl_regs = base + ETSEC_CTRL_REGS_OFFSET;

		ptp_qoriq->regs.alarm_regs = base + ETSEC_ALARM_REGS_OFFSET;

		ptp_qoriq->regs.fiper_regs = base + ETSEC_FIPER_REGS_OFFSET;

		ptp_qoriq->regs.etts_regs = base + ETSEC_ETTS_REGS_OFFSET;

	} else {

		ptp_qoriq->regs.ctrl_regs = base + CTRL_REGS_OFFSET;

		ptp_qoriq->regs.alarm_regs = base + ALARM_REGS_OFFSET;

include/linux/fsl/ptp_qoriq.h

+9 −9
Original line number Diff line number Diff line
@@ -58,15 +58,15 @@ struct ptp_qoriq_registers { 
};



/* Offset definitions for the four register groups */

#define CTRL_REGS_OFFSET	0x0

#define ALARM_REGS_OFFSET	0x40

#define FIPER_REGS_OFFSET	0x80

#define ETTS_REGS_OFFSET	0xa0



#define FMAN_CTRL_REGS_OFFSET	0x80

#define FMAN_ALARM_REGS_OFFSET	0xb8

#define FMAN_FIPER_REGS_OFFSET	0xd0

#define FMAN_ETTS_REGS_OFFSET	0xe0

#define ETSEC_CTRL_REGS_OFFSET	0x0

#define ETSEC_ALARM_REGS_OFFSET	0x40

#define ETSEC_FIPER_REGS_OFFSET	0x80

#define ETSEC_ETTS_REGS_OFFSET	0xa0



#define CTRL_REGS_OFFSET	0x80

#define ALARM_REGS_OFFSET	0xb8

#define FIPER_REGS_OFFSET	0xd0

#define ETTS_REGS_OFFSET	0xe0





/* Bit definitions for the TMR_CTRL register */

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