Commit d4db5721 authored Jun 20, 2020 by Martin Blumenstingl Committed by Jerome Brunet Jun 24, 2020

clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2

Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't
know the relation between this clock and RGMII Ethernet. It turns out
that fclk_div2 is used as "timing adjustment clock" to generate the RX
delay on the MAC side - which was enabled by u-boot on Odriod-C1. When
using the RX delay on the PHY side or not using a RX delay at all then
this clock can be disabled.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200620161422.24114-1-martin.blumenstingl@googlemail.com

parent 2f1efa53

drivers/clk/meson/meson8b.c

+0 −7

Original line number	Diff line number	Diff line
		@@ -293,13 +293,6 @@ static struct clk_regmap meson8b_fclk_div2 = {
		&meson8b_fclk_div2_div.hw
		},
		.num_parents = 1,
		/*
		* FIXME: Ethernet with a RGMII PHYs is not working if
		* fclk_div2 is disabled. it is currently unclear why this
		* is. keep it enabled until the Ethernet driver knows how
		* to manage this clock.
		*/
		.flags = CLK_IS_CRITICAL,
		},
		};