Commit d4db4e55 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull new ARM SoC support from Arnd Bergmann:
 "There are three SoC families newly dded to the 32-bit and 64-bit Arm
  architecture code in the kernel this time:

   - Daniel Palmer adds initial support for two chips made by MStar, a
     taiwanese SoC manufacturer that became part of Mediatek in 2012.

     For now, the added support is fairly minimal, with just two of its
     Cortex-A7 based 32-bit camera chips getting support for a limited
     set of on-chip peripherals.

   - Lars Povlsen from Microchip adds support for their new Sparx5
     family of ethernet switch chips using 64-bit Cortex-A53 cores.

     These are descended from earlier VSC7xxx SparX and Ocelot chips
     using 32-bit MIPS cores.

   - Daniele Alessandrelli from Intel adds support for the new Keem Bay
     SoC for computer vision, built around a Movidius VPU with Linux
     running on Arm Cortex-A53 cores"

* tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
  ARM: mstar: Correct the compatible string for pmsleep
  dt-bindings: arm: mstar: remove the binding description for mstar,pmsleep
  dt-bindings: mfd: syscon: add compatible string for mstar,msc313-pmsleep
  ARM: mstar: Add reboot support
  ARM: mstar: Add "pmsleep" node to base dtsi
  ARM: mstar: Add PMU
  ARM: mstar: Adjust IMI size for infinity3
  ARM: mstar: Adjust IMI size for mercury5
  ARM: mstar: Adjust IMI size of infinity
  ARM: mstar: Add IMI SRAM region
  dt-bindings: arm: mstar: Move existing MStar binding descriptions
  dt-bindings: arm: mstar: Add binding details for mstar, pmsleep
  ARM: mstar: Fix dts filename for 70mai midrive d08
  ARM: mstar: Add dts for 70mai midrive d08
  ARM: mstar: Add dts for msc313(e) based BreadBee boards
  ARM: mstar: Add mercury5 series dtsis
  ARM: mstar: Add infinity/infinity3 family dtsis
  ARM: mstar: Add Armv7 base dtsi
  ARM: mstar: Add binding details for mstar,l3bridge
  ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs
  ...
parents 822ef14e 892900a7

Documentation/devicetree/bindings/arm/intel,keembay.yaml

0 → 100644
+19 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/intel,keembay.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Keem Bay platform device tree bindings



maintainers:

  - Paul J. Murphy <paul.j.murphy@intel.com>

  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>



properties:

  compatible:

    items:

      - enum:

        - intel,keembay-evm

      - const: intel,keembay

...

Documentation/devicetree/bindings/arm/microchip,sparx5.yaml

0 → 100644
+65 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip Sparx5 Boards Device Tree Bindings



maintainers:

  - Lars Povlsen <lars.povlsen@microchip.com>



description: |+

   The Microchip Sparx5 SoC is a ARMv8-based used in a family of

   gigabit TSN-capable gigabit switches.



   The SparX-5 Ethernet switch family provides a rich set of switching

   features such as advanced TCAM-based VLAN and QoS processing

   enabling delivery of differentiated services, and security through

   TCAM-based frame processing using versatile content aware processor

   (VCAP)



properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:

      - description: The Sparx5 pcb125 board is a modular board,

          which has both spi-nor and eMMC storage. The modular design

          allows for connection of different network ports.

        items:

          - const: microchip,sparx5-pcb125

          - const: microchip,sparx5



      - description: The Sparx5 pcb134 is a pizzabox form factor

          gigabit switch with 20 SFP ports. It features spi-nor and

          either spi-nand or eMMC storage (mount option).

        items:

          - const: microchip,sparx5-pcb134

          - const: microchip,sparx5



      - description: The Sparx5 pcb135 is a pizzabox form factor

          gigabit switch with 48+4 Cu ports. It features spi-nor and

          either spi-nand or eMMC storage (mount option).

        items:

          - const: microchip,sparx5-pcb135

          - const: microchip,sparx5



  axi@600000000:

    type: object

    description: the root node in the Sparx5 platforms must contain

      an axi bus child node. They are always at physical address

      0x600000000 in all the Sparx5 variants.

    properties:

      compatible:

        items:

          - const: simple-bus



    required:

      - compatible



required:

  - compatible

  - axi@600000000



...

Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml

0 → 100644
+44 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2020 thingy.jp.

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: MStar/SigmaStar Armv7 SoC l3bridge



maintainers:

  - Daniel Palmer <daniel@thingy.jp>



description: |

  MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface

  between the CPU and memory. This means that before DMA capable

  devices are allowed to run the pipeline must be flushed to ensure

  everything is in memory.



  The l3bridge region contains registers that allow such a flush

  to be triggered.



  This node is used by the platform code to find where the registers

  are and install a barrier that triggers the required pipeline flush.



properties:

  compatible:

    items:

      - const: mstar,l3bridge



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    l3bridge: l3bridge@1f204400 {

        compatible = "mstar,l3bridge";

        reg = <0x1f204400 0x200>;

    };

Documentation/devicetree/bindings/arm/mstar/mstar.yaml

0 → 100644
+33 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/mstar/mstar.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MStar platforms device tree bindings



maintainers:

  - Daniel Palmer <daniel@thingy.jp>



properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:

      - description: infinity boards

        items:

          - enum:

              - thingyjp,breadbee-crust # thingy.jp BreadBee Crust

          - const: mstar,infinity



      - description: infinity3 boards

        items:

          - enum:

              - thingyjp,breadbee # thingy.jp BreadBee

          - const: mstar,infinity3



      - description: mercury5 boards

        items:

          - enum:

              - 70mai,midrived08 # 70mai midrive d08

          - const: mstar,mercury5

Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml

0 → 100644
+52 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip Sparx5 DPLL Clock



maintainers:

  - Lars Povlsen <lars.povlsen@microchip.com>



description: |

  The Sparx5 DPLL clock controller generates and supplies clock to

  various peripherals within the SoC.



properties:

  compatible:

    const: microchip,sparx5-dpll



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  # Clock provider for eMMC:

  - |

    lcpll_clk: lcpll-clk {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <2500000000>;

    };

    clks: clock-controller@61110000c {

        compatible = "microchip,sparx5-dpll";

        #clock-cells = <1>;

        clocks = <&lcpll_clk>;

        reg = <0x1110000c 0x24>;

    };



...

CRA Git | Maintained and supported by SUSTech CRA and CCSE