Commit d4c5792e authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
Browse files

clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m 



i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
NOT sys_pll1_800m, correct it.

Fixes: ba5625c3 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent d52fb019

drivers/clk/imx/clk-imx8mm.c

+1 −1
Original line number Diff line number Diff line
@@ -293,7 +293,7 @@ static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_1 
					 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };



static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",

					 "video_pll1_out", "sys_pll1_800m", "audio_pll1_out", "clk_ext1" };

					 "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };



static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",

					 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };

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