Commit d4b0c97a authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'qcom-drivers-for-5.5' of... 

Merge tag 'qcom-drivers-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers

Qualcomm ARM Based Driver Updates for v5.5

* Add Bjorn as QCOM co-maintainer
* Add LLLC yaml bindings and SC7180 support
* Fixups/Cleanup for LLLC
* Add SMD-RPM MSM8976 compatible and interconnect device
* Add missing RPMD SMD perf level

* tag 'qcom-drivers-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  MAINTAINERS: Add myself as co-maintainer for QCOM
  dt-bindings: msm: Add LLCC for SC7180
  dt-bindings: msm: Convert LLCC bindings to YAML
  soc: qcom: llcc: Add configuration data for SC7180
  soc: qcom: llcc: Move regmap config to local variable
  soc: qcom: llcc: Name regmaps to avoid collisions
  soc: qcom: Fix llcc-qcom definitions to include
  soc: qcom: rpmpd: Add rpm power domains for msm8976
  dt-bindings: power: Add missing rpmpd smd performance level
  soc: qcom: smd-rpm: Add MSM8976 compatible
  soc: qcom: socinfo: add sdm845 and sda845 soc ids
  soc: qcom: smd-rpm: Create RPM interconnect proxy child device
  soc: qcom: Make llcc-qcom a generic driver
  soc: qcom: Rename llcc-slice to llcc-qcom
  soc: qcom: llcc cleanup to get rid of sdm845 specific driver file

Link: https://lore.kernel.org/r/1573068840-13098-4-git-send-email-agross@kernel.org


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 8cbbff3a 971112e0

Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt

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== Introduction==



LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,

that can be shared by multiple clients. Clients here are different cores in the

SOC, the idea is to minimize the local caches at the clients and migrate to

common pool of memory. Cache memory is divided into partitions called slices

which are assigned to clients. Clients can query the slice details, activate

and deactivate them.



Properties:

- compatible:

	Usage: required

	Value type: <string>

	Definition: must be "qcom,sdm845-llcc"



- reg:

	Usage: required

	Value Type: <prop-encoded-array>

	Definition: The first element specifies the llcc base start address and

		    the size of the register region. The second element specifies

		    the llcc broadcast base address and size of the register region.



- reg-names:

        Usage: required

        Value Type: <stringlist>

        Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".



- interrupts:

	Usage: required

	Definition: The interrupt is associated with the llcc edac device.

			It's used for llcc cache single and double bit error detection

			and reporting.



Example:



	cache-controller@1100000 {

		compatible = "qcom,sdm845-llcc";

		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;

		reg-names = "llcc_base", "llcc_broadcast_base";

		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

	};

Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Last Level Cache Controller



maintainers:

  - Rishabh Bhatnagar <rishabhb@codeaurora.org>

  - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>



description: |

  LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,

  that can be shared by multiple clients. Clients here are different cores in the

  SoC, the idea is to minimize the local caches at the clients and migrate to

  common pool of memory. Cache memory is divided into partitions called slices

  which are assigned to clients. Clients can query the slice details, activate

  and deactivate them.



properties:

  compatible:

    enum:

      - qcom,sc7180-llcc

      - qcom,sdm845-llcc



  reg:

    items:

      - description: LLCC base register region

      - description: LLCC broadcast base register region



  reg-names:

    items:

      - const: llcc_base

      - const: llcc_broadcast_base



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - reg-names

  - interrupts



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    cache-controller@1100000 {

      compatible = "qcom,sdm845-llcc";

      reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;

      reg-names = "llcc_base", "llcc_broadcast_base";

      interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

    };

Documentation/devicetree/bindings/power/qcom,rpmpd.txt

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@@ -5,6 +5,7 @@ which then translates it into a corresponding voltage on a rail 


Required Properties:

 - compatible: Should be one of the following

	* qcom,msm8976-rpmpd: RPM Power domain for the msm8976 family of SoC

	* qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC

	* qcom,msm8998-rpmpd: RPM Power domain for the msm8998 family of SoC

	* qcom,qcs404-rpmpd: RPM Power domain for the qcs404 family of SoC

Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt

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@@ -22,6 +22,7 @@ resources. 
		    "qcom,rpm-apq8084"

		    "qcom,rpm-msm8916"

		    "qcom,rpm-msm8974"

		    "qcom,rpm-msm8976"

		    "qcom,rpm-msm8998"

		    "qcom,rpm-sdm660"

		    "qcom,rpm-qcs404"

MAINTAINERS

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@@ -2102,6 +2102,7 @@ S: Maintained 














ARM/QUALCOMM SUPPORT















M:	Andy Gross <agross@kernel.org>













M:	Bjorn Andersson <bjorn.andersson@linaro.org>















L:	linux-arm-msm@vger.kernel.org















S:	Maintained















F:	Documentation/devicetree/bindings/soc/qcom/









































































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