Commit d49d92ac authored Feb 05, 2019 by Chen-Yu Tsai Committed by Ulf Hansson Feb 06, 2019

mmc: sunxi: Disable HS-DDR mode for H5 eMMC controller by default



Some H5 boards seem to not have proper trace lengths for eMMC to be able
to use the default setting for the delay chains under HS-DDR mode. These
include the Bananapi M2+ H5 and NanoPi NEO Core2. However the Libre
Computer ALL-H3-CC-H5 works just fine.

For the H5 (at least for now), default to not enabling HS-DDR modes in
the driver, and expect the device tree to signal HS-DDR capability on
boards that work.

Reported-by: Chris Blake <chrisrblake93@gmail.com>
Fixes: 07bafc1e ("mmc: sunxi: Use new timing mode for A64 eMMC controller")
Cc: <stable@vger.kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

parent 8834f560

drivers/mmc/host/sunxi-mmc.c

+10 −1

Original line number	Diff line number	Diff line
		@@ -1399,7 +1399,16 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
		mmc->caps \|= MMC_CAP_MMC_HIGHSPEED \| MMC_CAP_SD_HIGHSPEED \|
		MMC_CAP_ERASE \| MMC_CAP_SDIO_IRQ;

		if (host->cfg->clk_delays \|\| host->use_new_timings)
		/*
		* Some H5 devices do not have signal traces precise enough to
		* use HS DDR mode for their eMMC chips.
		*
		* We still enable HS DDR modes for all the other controller
		* variants that support them.
		*/
		if ((host->cfg->clk_delays \|\| host->use_new_timings) &&
		!of_device_is_compatible(pdev->dev.of_node,
		"allwinner,sun50i-h5-emmc"))
		mmc->caps \|= MMC_CAP_1_8V_DDR \| MMC_CAP_3_3V_DDR;

		ret = mmc_of_parse(mmc);

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