Commit d4786672 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: use odm combine for YCbCr420 timing with h_active greater than 4096 



[why]
FMT has limitation to support YCbCr420 with h_active greater than 4096.

[how]
Use odm combine to overcome the limitation.

Signed-off-by: default avatarWenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 09f6dd6e

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

+13 −6
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 


#define BPP_INVALID 0

#define BPP_BLENDED_PIPE 0xffffffff

#define DCN20_MAX_420_IMAGE_WIDTH 4096



static double adjust_ReturnBW(

		struct display_mode_lib *mode_lib,
@@ -3894,13 +3895,19 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
						&& i == mode_lib->vba.soc.num_states)

					mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2

							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);

				if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {



				locals->ODMCombineEnablePerState[i][k] = false;

				mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;

				} else {

				if (mode_lib->vba.ODMCapability) {

					if (locals->PlaneRequiredDISPCLKWithoutODMCombine > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {

						locals->ODMCombineEnablePerState[i][k] = true;

						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;

					} else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {

						locals->ODMCombineEnablePerState[i][k] = true;

						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;

					}

				}



				if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity

						&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]

						&& locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

+16 −8
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
#define BPP_INVALID 0

#define BPP_BLENDED_PIPE 0xffffffff

#define DCN20_MAX_DSC_IMAGE_WIDTH 5184

#define DCN20_MAX_420_IMAGE_WIDTH 4096



static double adjust_ReturnBW(

		struct display_mode_lib *mode_lib,
@@ -3935,15 +3936,22 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode 
						&& i == mode_lib->vba.soc.num_states)

					mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2

							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);

				if (mode_lib->vba.ODMCapability == false ||

						(locals->PlaneRequiredDISPCLKWithoutODMCombine <= MaxMaxDispclkRoundedDown

							&& (!locals->DSCEnabled[k] || locals->HActive[k] <= DCN20_MAX_DSC_IMAGE_WIDTH))) {



				locals->ODMCombineEnablePerState[i][k] = false;

				mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;

				} else {

				if (mode_lib->vba.ODMCapability) {

					if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) {

						locals->ODMCombineEnablePerState[i][k] = true;

						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;

					} else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN20_MAX_DSC_IMAGE_WIDTH)) {

						locals->ODMCombineEnablePerState[i][k] = true;

						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;

					} else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {

						locals->ODMCombineEnablePerState[i][k] = true;

						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;

					}

				}



				if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity

						&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]

						&& locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

+16 −8
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ typedef struct { 
#define BPP_INVALID 0

#define BPP_BLENDED_PIPE 0xffffffff

#define DCN21_MAX_DSC_IMAGE_WIDTH 5184

#define DCN21_MAX_420_IMAGE_WIDTH 4096



static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);

static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
@@ -3971,15 +3972,22 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
						&& i == mode_lib->vba.soc.num_states)

					mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2

							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);

				if (mode_lib->vba.ODMCapability == false ||

						(locals->PlaneRequiredDISPCLKWithoutODMCombine <= MaxMaxDispclkRoundedDown

							&& (!locals->DSCEnabled[k] || locals->HActive[k] <= DCN21_MAX_DSC_IMAGE_WIDTH))) {



				locals->ODMCombineEnablePerState[i][k] = false;

				mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;

				} else {

				if (mode_lib->vba.ODMCapability) {

					if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) {

						locals->ODMCombineEnablePerState[i][k] = true;

						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;

					} else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN21_MAX_DSC_IMAGE_WIDTH)) {

						locals->ODMCombineEnablePerState[i][k] = true;

						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;

					} else if (locals->HActive[k] > DCN21_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {

						locals->ODMCombineEnablePerState[i][k] = true;

						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;

					}

				}



				if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity

						&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]

						&& locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {

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