drm/amd/display: Update hdcp display config (d462fcf5) · Commits · 戴 / test

drivers/gpu/drm/amd/display/dc/core/dc.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -830,6 +830,16 @@ void dc_hardware_init(struct dc *dc)
		void dc_init_callbacks(struct dc *dc,
		const struct dc_callback_init *init_params)
		{
		#ifdef CONFIG_DRM_AMD_DC_HDCP
		dc->ctx->cp_psp = init_params->cp_psp;
		#endif
		}

		void dc_deinit_callbacks(struct dc *dc)
		{
		#ifdef CONFIG_DRM_AMD_DC_HDCP
		memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
		#endif
		}

		void dc_destroy(struct dc **dc)

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+31 −0

Original line number	Diff line number	Diff line
		@@ -2690,6 +2690,24 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)

		return DC_OK;
		}
		#if defined(CONFIG_DRM_AMD_DC_HDCP)
		static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
		{
		struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
		if (cp_psp && cp_psp->funcs.update_stream_config) {
		struct cp_psp_stream_config config;

		memset(&config, 0, sizeof(config));

		config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
		config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->id;
		config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
		config.dpms_off = dpms_off;
		config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
		cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
		}
		}
		#endif

		void core_link_enable_stream(
		struct dc_state *state,
		@@ -2750,6 +2768,9 @@ void core_link_enable_stream(
		/* Do not touch link on seamless boot optimization. */
		if (pipe_ctx->stream->apply_seamless_boot_optimization) {
		pipe_ctx->stream->dpms_off = false;
		#if defined(CONFIG_DRM_AMD_DC_HDCP)
		update_psp_stream_config(pipe_ctx, false);
		#endif
		return;
		}

		@@ -2757,6 +2778,9 @@ void core_link_enable_stream(
		if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
		apply_edp_fast_boot_optimization) {
		pipe_ctx->stream->dpms_off = false;
		#if defined(CONFIG_DRM_AMD_DC_HDCP)
		update_psp_stream_config(pipe_ctx, false);
		#endif
		return;
		}

		@@ -2816,6 +2840,9 @@ void core_link_enable_stream(

		if (dc_is_dp_signal(pipe_ctx->stream->signal))
		enable_stream_features(pipe_ctx);
		#if defined(CONFIG_DRM_AMD_DC_HDCP)
		update_psp_stream_config(pipe_ctx, false);
		#endif
		}
		#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
		else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
		@@ -2833,6 +2860,10 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
		struct dc_stream_state *stream = pipe_ctx->stream;
		struct dc_link *link = stream->sink->link;

		#if defined(CONFIG_DRM_AMD_DC_HDCP)
		update_psp_stream_config(pipe_ctx, true);
		#endif

		core_dc->hwss.blank_stream(pipe_ctx);

		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

drivers/gpu/drm/amd/display/dc/dc.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -552,7 +552,11 @@ struct dc_init_data {
		};

		struct dc_callback_init {
		#ifdef CONFIG_DRM_AMD_DC_HDCP
		struct cp_psp cp_psp;
		#else
		uint8_t reserved;
		#endif
		};

		struct dc dc_create(const struct dc_init_data init_params);
		@@ -566,6 +570,7 @@ int dc_setup_system_context(struct dc dc, struct dc_phy_addr_space_config pa_c
		#endif
		void dc_init_callbacks(struct dc *dc,
		const struct dc_callback_init *init_params);
		void dc_deinit_callbacks(struct dc *dc);
		void dc_destroy(struct dc **dc);

		/*******************************************************************************

drivers/gpu/drm/amd/display/dc/dc_types.h

+7 −0

Original line number	Diff line number	Diff line
		@@ -38,6 +38,10 @@
		#include "dal_types.h"
		#include "grph_object_defs.h"

		#ifdef CONFIG_DRM_AMD_DC_HDCP
		#include "dm_cp_psp.h"
		#endif

		/* forward declarations */
		struct dc_plane_state;
		struct dc_stream_state;
		@@ -105,6 +109,9 @@ struct dc_context {
		uint32_t dc_sink_id_count;
		uint32_t dc_stream_id_count;
		uint64_t fbc_gpu_addr;
		#ifdef CONFIG_DRM_AMD_DC_HDCP
		struct cp_psp cp_psp;
		#endif
		};

drivers/gpu/drm/amd/display/dc/dm_cp_psp.h

0 → 100644

+49 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2018 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		* Authors: AMD
		*
		*/

		#ifndef DM_CP_PSP_IF__H
		#define DM_CP_PSP_IF__H

		struct dc_link;

		struct cp_psp_stream_config {
		uint8_t otg_inst;
		uint8_t link_enc_inst;
		uint8_t stream_enc_inst;
		void *dm_stream_ctx;
		bool dpms_off;
		};

		struct cp_psp_funcs {
		void (update_stream_config)(void handle, struct cp_psp_stream_config *config);
		};

		struct cp_psp {
		void *handle;
		struct cp_psp_funcs funcs;
		};


		#endif /* DM_CP_PSP_IF__H */

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