net: ethernet: mediatek: Add MT7629 ethernet support (d438e298) · Commits · 戴 / test

drivers/net/ethernet/mediatek/mtk_eth_soc.c

+12 −2

Original line number	Diff line number	Diff line
		@@ -54,8 +54,10 @@ static const struct mtk_ethtool_stats {
		};

		static const char * const mtk_clks_source_name[] = {
		"ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m",
		"sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll"
		"ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
		"sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
		"sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
		"sgmii_ck", "eth2pll",
		};

		void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
		@@ -2628,11 +2630,19 @@ static const struct mtk_soc_data mt7623_data = {
		.required_pctl = true,
		};

		static const struct mtk_soc_data mt7629_data = {
		.ana_rgc3 = 0x128,
		.caps = MT7629_CAPS \| MTK_HWLRO,
		.required_clks = MT7629_CLKS_BITMAP,
		.required_pctl = false,
		};

		const struct of_device_id of_mtk_match[] = {
		{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
		{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
		{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
		{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
		{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
		{},
		};
		MODULE_DEVICE_TABLE(of, of_mtk_match);

+19 −0

Original line number	Diff line number	Diff line
		@@ -475,15 +475,21 @@ enum mtk_tx_flags {
		*/
		enum mtk_clks_map {
		MTK_CLK_ETHIF,
		MTK_CLK_SGMIITOP,
		MTK_CLK_ESW,
		MTK_CLK_GP0,
		MTK_CLK_GP1,
		MTK_CLK_GP2,
		MTK_CLK_FE,
		MTK_CLK_TRGPLL,
		MTK_CLK_SGMII_TX_250M,
		MTK_CLK_SGMII_RX_250M,
		MTK_CLK_SGMII_CDR_REF,
		MTK_CLK_SGMII_CDR_FB,
		MTK_CLK_SGMII2_TX_250M,
		MTK_CLK_SGMII2_RX_250M,
		MTK_CLK_SGMII2_CDR_REF,
		MTK_CLK_SGMII2_CDR_FB,
		MTK_CLK_SGMII_CK,
		MTK_CLK_ETH2PLL,
		MTK_CLK_MAX
		@@ -502,6 +508,19 @@ enum mtk_clks_map {
		BIT(MTK_CLK_SGMII_CK) \| \
		BIT(MTK_CLK_ETH2PLL))
		#define MT7621_CLKS_BITMAP (0)
		#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) \| BIT(MTK_CLK_ESW) \| \
		BIT(MTK_CLK_GP0) \| BIT(MTK_CLK_GP1) \| \
		BIT(MTK_CLK_GP2) \| BIT(MTK_CLK_FE) \| \
		BIT(MTK_CLK_SGMII_TX_250M) \| \
		BIT(MTK_CLK_SGMII_RX_250M) \| \
		BIT(MTK_CLK_SGMII_CDR_REF) \| \
		BIT(MTK_CLK_SGMII_CDR_FB) \| \
		BIT(MTK_CLK_SGMII2_TX_250M) \| \
		BIT(MTK_CLK_SGMII2_RX_250M) \| \
		BIT(MTK_CLK_SGMII2_CDR_REF) \| \
		BIT(MTK_CLK_SGMII2_CDR_FB) \| \
		BIT(MTK_CLK_SGMII_CK) \| \
		BIT(MTK_CLK_ETH2PLL) \| BIT(MTK_CLK_SGMIITOP))

		enum mtk_dev_state {
		MTK_HW_INIT,