Commit d43628e9 authored by Neil Armstrong's avatar Neil Armstrong Committed by Jerome Brunet
Browse files

clk: meson: g12a: Add support for G12B CPUB clocks 



Update the Meson G12A Clock driver to support the Amlogic G12B SoC.

G12B clock driver is very close, the main differences are :
- the clock tree is duplicated for the both clusters, and the
  SYS_PLL are swapped between the clusters
- G12B has additional clocks like for CSI an other components

Here only the cpu clock tree is handled.

Reviewed-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 1360952c

drivers/clk/meson/g12a.c

+792 −30

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/meson/g12a.h

+39 −1
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ 
#define HHI_VDEC4_CLK_CNTL		0x1EC

#define HHI_HDCP22_CLK_CNTL		0x1F0

#define HHI_VAPBCLK_CNTL		0x1F4

#define HHI_SYS_CPUB_CLK_CNTL1		0x200

#define HHI_SYS_CPUB_CLK_CNTL		0x208

#define HHI_VPU_CLKB_CNTL		0x20C

#define HHI_GEN_CLK_CNTL		0x228

#define HHI_VDIN_MEAS_CLK_CNTL		0x250
@@ -102,6 +104,13 @@ 
#define HHI_HDMI_PLL_CNTL5		0x334

#define HHI_HDMI_PLL_CNTL6		0x338

#define HHI_SPICC_CLK_CNTL		0x3dc

#define HHI_SYS1_PLL_CNTL0		0x380

#define HHI_SYS1_PLL_CNTL1		0x384

#define HHI_SYS1_PLL_CNTL2		0x388

#define HHI_SYS1_PLL_CNTL3		0x38c

#define HHI_SYS1_PLL_CNTL4		0x390

#define HHI_SYS1_PLL_CNTL5		0x394

#define HHI_SYS1_PLL_CNTL6		0x398



/*

 * CLKID index values
@@ -196,8 +205,37 @@ 
#define CLKID_VDEC_HEVCF_SEL			208

#define CLKID_VDEC_HEVCF_DIV			209

#define CLKID_TS_DIV				211

#define CLKID_SYS1_PLL_DCO			213

#define CLKID_SYS1_PLL				214

#define CLKID_SYS1_PLL_DIV16_EN			215

#define CLKID_SYS1_PLL_DIV16			216

#define CLKID_CPUB_CLK_DYN0_SEL			217

#define CLKID_CPUB_CLK_DYN0_DIV			218

#define CLKID_CPUB_CLK_DYN0			219

#define CLKID_CPUB_CLK_DYN1_SEL			220

#define CLKID_CPUB_CLK_DYN1_DIV			221

#define CLKID_CPUB_CLK_DYN1			222

#define CLKID_CPUB_CLK_DYN			223

#define CLKID_CPUB_CLK				224

#define CLKID_CPUB_CLK_DIV16_EN			225

#define CLKID_CPUB_CLK_DIV16			226

#define CLKID_CPUB_CLK_DIV2			227

#define CLKID_CPUB_CLK_DIV3			228

#define CLKID_CPUB_CLK_DIV4			229

#define CLKID_CPUB_CLK_DIV5			230

#define CLKID_CPUB_CLK_DIV6			231

#define CLKID_CPUB_CLK_DIV7			232

#define CLKID_CPUB_CLK_DIV8			233

#define CLKID_CPUB_CLK_APB_SEL			234

#define CLKID_CPUB_CLK_APB			235

#define CLKID_CPUB_CLK_ATB_SEL			236

#define CLKID_CPUB_CLK_ATB			237

#define CLKID_CPUB_CLK_AXI_SEL			238

#define CLKID_CPUB_CLK_AXI			239

#define CLKID_CPUB_CLK_TRACE_SEL		240

#define CLKID_CPUB_CLK_TRACE			241



#define NR_CLKS					213

#define NR_CLKS					242



/* include the CLKIDs that have been made part of the DT binding */

#include <dt-bindings/clock/g12a-clkc.h>

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