Commit d4324ce3 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'mvebu-soc-3.15-2' of git://git.infradead.org/linux-mvebu into next/soc 

Merge "mvebu soc changes for v3.15 (incremental pull #2)" from Jason Cooper:

 - mvebu
    - Add Armada 375, 380 and 385 SoCs

 - kirkwood
    - move kirkwood DT support to mach-mvebu
    - add mostly DT support for HP T5325 thin client

* tag 'mvebu-soc-3.15-2' of git://git.infradead.org/linux-mvebu

:
  ARM: kirkwood: Add HP T5325 thin client
  ARM: kirkwood: select dtbs based on SoC
  ARM: kirkwood: Remove redundant kexec code
  ARM: mvebu: Armada 375/38x depend on MULTI_V7
  ARM: mvebu: Simplify headers and make local
  ARM: mvebu: Enable mvebu-soc-id on Kirkwood
  ARM: mvebu: Let kirkwood use the system controller for restart
  ARM: mvebu: Move kirkwood DT boards into mach-mvebu
  ARM: MM Enable building Feroceon L2 cache controller with ARCH_MVEBU
  ARM: Fix default CPU selection for ARCH_MULTI_V5
  ARM: MM: Add DT binding for Feroceon L2 cache
  ARM: orion: Move cache-feroceon-l2.h out of plat-orion
  ARM: mvebu: Add ARCH_MULTI_V7 to SoCs
  ARM: kirkwood: ioremap memory control register
  ARM: kirkwood: ioremap the cpu_config register before using it.
  ARM: kirkwood: Separate board-dt from common and pcie code.
  ARM: kirkwood: Drop printing the SoC type and revision
  ARM: kirkwood: Convert mv88f6281gtw_ge switch setup to DT
  ARM: kirkwood: Give pm.c its own header file.
  ARM: mvebu: Rename the ARCH_MVEBU menu option

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 56f55deb 0d75ab68

Documentation/devicetree/bindings/arm/mrvl/feroceon.txt

0 → 100644
+16 −0
Original line number Diff line number Diff line 
* Marvell Feroceon Cache



Required properties:

- compatible : Should be either "marvell,feroceon-cache" or

  	       "marvell,kirkwood-cache".



Optional properties:

- reg        : Address of the L2 cache control register. Mandatory for

  	       "marvell,kirkwood-cache", not used by "marvell,feroceon-cache"





Example:

		l2: l2-cache@20128 {

			compatible = "marvell,kirkwood-cache";

			reg = <0x20128 0x4>;

		};

arch/arm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -898,7 +898,7 @@ config ARCH_MULTI_V5 
	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"

	depends on !ARCH_MULTI_V6_V7

	select ARCH_MULTI_V4_V5

	select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \

	select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \

		CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \

		CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)

arch/arm/boot/dts/Makefile

+5 −2
Original line number Diff line number Diff line
@@ -82,8 +82,8 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 
	ecx-2000.dtb

dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \

	integratorcp.dtb

dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb

dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \

kirkwood := \

	kirkwood-cloudbox.dtb \

	kirkwood-db-88f6281.dtb \

	kirkwood-db-88f6282.dtb \

	kirkwood-dns320.dtb \
@@ -117,6 +117,9 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ 
	kirkwood-topkick.dtb \

	kirkwood-ts219-6281.dtb \

	kirkwood-ts219-6282.dtb

dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood)

dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood)

dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb

dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb

dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb

dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \

arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts

+62 −0
Original line number Diff line number Diff line
@@ -122,4 +122,66 @@ 
			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;

		};

	};



	dsa@0 {

		compatible = "marvell,dsa";

		#address-cells = <2>;

		#size-cells = <0>;



		dsa,ethernet = <&eth0>;

		dsa,mii-bus = <&ethphy0>;



		switch@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */



			port@0 {

				reg = <0>;

				label = "lan1";

			};



			port@1 {

				reg = <1>;

				label = "lan2";

			};



			port@2 {

				reg = <2>;

				label = "lan3";

			};



			port@3 {

				reg = <3>;

				label = "lan4";

			};



			port@4 {

				reg = <4>;

				label = "wan";

			};



			port@5 {

				reg = <5>;

				label = "cpu";

			};

		};

	};

};



&mdio {

	status = "okay";



	ethphy0: ethernet-phy@ff {

		reg = <0xff>; 	/* No phy attached */

		speed = <1000>;

		duplex = <1>;

	};

};



&eth0 {

	status = "okay";

	ethernet0-port@0 {

		phy-handle = <&ethphy0>;

	};

};

arch/arm/plat-orion/include/plat/cache-feroceon-l2.h→arch/arm/include/asm/hardware/cache-feroceon-l2.h

+3 −1
Original line number Diff line number Diff line 
/*

 * arch/arm/plat-orion/include/plat/cache-feroceon-l2.h

 * arch/arm/include/asm/hardware/cache-feroceon-l2.h

 *

 * Copyright (C) 2008 Marvell Semiconductor

 *
@@ -9,3 +9,5 @@ 
 */



extern void __init feroceon_l2_init(int l2_wt_override);

extern int __init feroceon_of_init(void);

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