Commit d4292518 authored by Ryder Lee's avatar Ryder Lee Committed by Stephen Boyd
Browse files

clk: mediatek: fix the PCIe MAC clock parent 



The PCIe function doesn't work as the clock tree of MAC layer is wrong.
Hence fix the clock table.

Fixes: 3b5e7486 ("clk: mediatek: add clock support for MT7629 SoC")
Signed-off-by: default avatarRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 553604c0

drivers/clk/mediatek/clk-mt7629.c

+2 −2
Original line number Diff line number Diff line
@@ -446,8 +446,8 @@ static const struct mtk_fixed_factor top_divs[] = { 
	FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1),

	FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1),

	FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1),

	FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),

	FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),

	FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "sata_sel", 1, 1),

	FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "sata_sel", 1, 1),

};



static const struct mtk_gate peri_clks[] = {

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