Commit d425e7d8 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: add some [WR]REG32_SDMA macros to sdma_v4_0.c 



Significantly shortens the code.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 998d3fd4

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+63 −63
Original line number Diff line number Diff line
@@ -54,6 +54,11 @@ MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 
#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L

#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L



#define WREG32_SDMA(instance, offset, value) \

	WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)

#define RREG32_SDMA(instance, offset) \

	RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))



static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);

static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);

static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
@@ -369,8 +374,8 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 
	} else {

		u32 lowbit, highbit;



		lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;

		highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;

		lowbit = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR) >> 2;

		highbit = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI) >> 2;



		DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",

				ring->me, highbit, lowbit);
@@ -417,8 +422,10 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 
				lower_32_bits(ring->wptr << 2),

				ring->me,

				upper_32_bits(ring->wptr << 2));

		WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

		WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

		WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,

			    lower_32_bits(ring->wptr << 2));

		WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,

			    upper_32_bits(ring->wptr << 2));

	}

}
@@ -568,12 +575,12 @@ static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 
			amdgpu_ttm_set_buffer_funcs_status(adev, false);



	for (i = 0; i < adev->sdma.num_instances; i++) {

		rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

		rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);

		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

		WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

		ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

		WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);

		ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);

		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);

		WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

		WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);

	}



	sdma0->ready = false;
@@ -630,18 +637,15 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 
	}



	for (i = 0; i < adev->sdma.num_instances; i++) {

		f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

		f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);

		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

				AUTO_CTXSW_ENABLE, enable ? 1 : 0);

		if (enable && amdgpu_sdma_phase_quantum) {

			WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),

			       phase_quantum);

			WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),

			       phase_quantum);

			WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),

			       phase_quantum);

			WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);

			WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);

			WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);

		}

		WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);

		WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);

	}



}
@@ -665,9 +669,9 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 
	}



	for (i = 0; i < adev->sdma.num_instances; i++) {

		f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

		f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);

		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

		WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);

		WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);

	}

}
@@ -694,39 +698,39 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 


	/* Set ring buffer size in dwords */

	rb_bufsz = order_base_2(ring->ring_size / 4);

	rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

	rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);

	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

#ifdef __BIG_ENDIAN

	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

				RPTR_WRITEBACK_SWAP_ENABLE, 1);

#endif

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

	WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);



	/* Initialize the ring buffer's read and write pointers */

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);

	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);

	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);

	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);

	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);



	/* set the wb address whether it's enabled or not */

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),

	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,

	       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),

	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,

	       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);



	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);



	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);

	WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);

	WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);



	ring->wptr = 0;



	/* before programing wptr to a less value, need set minor_ptr_update first */

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);

	WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);



	doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));

	doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));

	doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);

	doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);



	if (ring->use_doorbell) {

		doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
@@ -735,40 +739,40 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 
	} else {

		doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

	}

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);

	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);

	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);

	adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,

					      ring->doorbell_index);



	sdma_v4_0_ring_set_wptr(ring);



	/* set minor_ptr_update to 0 after wptr programed */

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);

	WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);



	/* setup the wptr shadow polling */

	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),

	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,

		    lower_32_bits(wptr_gpu_addr));

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),

	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,

		    upper_32_bits(wptr_gpu_addr));

	wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));

	wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);

	if (amdgpu_sriov_vf(adev))

		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);

	else

		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);

	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);



	/* enable DMA RB */

	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

	WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);



	ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

	ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);

	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);

#ifdef __BIG_ENDIAN

	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

#endif

	/* enable DMA IBs */

	WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

	WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);



	ring->ready = true;

}
@@ -881,12 +885,14 @@ static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 
			(adev->sdma.instance[i].fw->data +

				le32_to_cpu(hdr->header.ucode_array_offset_bytes));



		WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);

		WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);



		for (j = 0; j < fw_size; j++)

			WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));

			WREG32_SDMA(i, mmSDMA0_UCODE_DATA,

				    le32_to_cpup(fw_data++));



		WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);

		WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,

			    adev->sdma.instance[i].fw_version);

	}



	return 0;
@@ -926,22 +932,19 @@ static int sdma_v4_0_start(struct amdgpu_device *adev) 
	for (i = 0; i < adev->sdma.num_instances; i++) {

		uint32_t temp;



		WREG32(sdma_v4_0_get_reg_offset(adev, i,

				mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

		WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);

		sdma_v4_0_gfx_resume(adev, i);



		/* set utc l1 enable flag always to 1 */

		temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

		temp = RREG32_SDMA(i, mmSDMA0_CNTL);

		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);

		WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);

		WREG32_SDMA(i, mmSDMA0_CNTL, temp);



		if (!amdgpu_sriov_vf(adev)) {

			/* unhalt engine */

			temp = RREG32(sdma_v4_0_get_reg_offset(adev, i,

					mmSDMA0_F32_CNTL));

			temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);

			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

			WREG32(sdma_v4_0_get_reg_offset(adev, i,

					mmSDMA0_F32_CNTL), temp);

			WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);

		}

	}
@@ -1410,7 +1413,7 @@ static bool sdma_v4_0_is_idle(void *handle) 
	u32 i;



	for (i = 0; i < adev->sdma.num_instances; i++) {

		u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));

		u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);



		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))

			return false;
@@ -1426,8 +1429,8 @@ static int sdma_v4_0_wait_for_idle(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	for (i = 0; i < adev->usec_timeout; i++) {

		sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));

		sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));

		sdma0 = RREG32_SDMA(0, mmSDMA0_STATUS_REG);

		sdma1 = RREG32_SDMA(1, mmSDMA0_STATUS_REG);



		if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)

			return 0;
@@ -1448,16 +1451,13 @@ static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 
					unsigned type,

					enum amdgpu_interrupt_state state)

{

	unsigned int instance = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 0 : 1;

	u32 sdma_cntl;



	u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?

		sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :

		sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);



	sdma_cntl = RREG32(reg_offset);

	sdma_cntl = RREG32_SDMA(instance, mmSDMA0_CNTL);

	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);

	WREG32(reg_offset, sdma_cntl);

	WREG32_SDMA(instance, mmSDMA0_CNTL, sdma_cntl);



	return 0;

}

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