Commit d4225a53 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Syntatic sugar for using intel_runtime_pm 



Frequently, we use intel_runtime_pm_get/_put around a small block.
Formalise that usage by providing a macro to define such a block with an
automatic closure to scope the intel_runtime_pm wakeref to that block,
i.e. macro abuse smelling of python.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190114142129.24398-15-chris@chris-wilson.co.uk
parent c9d08cc3

drivers/gpu/drm/i915/i915_debugfs.c

+71 −91
Original line number Diff line number Diff line
@@ -953,9 +953,9 @@ static int i915_gpu_info_open(struct inode *inode, struct file *file) 
	struct i915_gpu_state *gpu;

	intel_wakeref_t wakeref;



	wakeref = intel_runtime_pm_get(i915);

	gpu = NULL;

	with_intel_runtime_pm(i915, wakeref)

		gpu = i915_capture_gpu_state(i915);

	intel_runtime_pm_put(i915, wakeref);

	if (IS_ERR(gpu))

		return PTR_ERR(gpu);
@@ -1287,16 +1287,14 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused) 
		return 0;

	}



	wakeref = intel_runtime_pm_get(dev_priv);



	with_intel_runtime_pm(dev_priv, wakeref) {

		for_each_engine(engine, dev_priv, id) {

			acthd[id] = intel_engine_get_active_head(engine);

			seqno[id] = intel_engine_get_seqno(engine);

		}



		intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);



	intel_runtime_pm_put(dev_priv, wakeref);

	}



	if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))

		seq_printf(m, "Hangcheck active, timer fires in %dms\n",
@@ -1573,18 +1571,16 @@ static int i915_drpc_info(struct seq_file *m, void *unused) 
{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	intel_wakeref_t wakeref;

	int err;



	wakeref = intel_runtime_pm_get(dev_priv);

	int err = -ENODEV;



	with_intel_runtime_pm(dev_priv, wakeref) {

		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

			err = vlv_drpc_info(m);

		else if (INTEL_GEN(dev_priv) >= 6)

			err = gen6_drpc_info(m);

		else

			err = ironlake_drpc_info(m);



	intel_runtime_pm_put(dev_priv, wakeref);

	}



	return err;

}
@@ -2068,8 +2064,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) 
	intel_wakeref_t wakeref;

	struct drm_file *file;



	wakeref = intel_runtime_pm_get_if_in_use(dev_priv);

	if (wakeref) {

	with_intel_runtime_pm_if_in_use(dev_priv, wakeref) {

		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

			mutex_lock(&dev_priv->pcu_lock);

			act_freq = vlv_punit_read(dev_priv,
@@ -2080,7 +2075,6 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) 
			act_freq = intel_get_cagf(dev_priv,

						  I915_READ(GEN6_RPSTAT1));

		}

		intel_runtime_pm_put(dev_priv, wakeref);

	}



	seq_printf(m, "RPS enabled? %d\n", rps->enabled);
@@ -2172,9 +2166,8 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data) 
	p = drm_seq_file_printer(m);

	intel_uc_fw_dump(&dev_priv->huc.fw, &p);



	wakeref = intel_runtime_pm_get(dev_priv);

	with_intel_runtime_pm(dev_priv, wakeref)

		seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));

	intel_runtime_pm_put(dev_priv, wakeref);



	return 0;

}
@@ -2184,7 +2177,6 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data) 
	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	intel_wakeref_t wakeref;

	struct drm_printer p;

	u32 tmp, i;



	if (!HAS_GUC(dev_priv))

		return -ENODEV;
@@ -2192,9 +2184,9 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data) 
	p = drm_seq_file_printer(m);

	intel_uc_fw_dump(&dev_priv->guc.fw, &p);



	wakeref = intel_runtime_pm_get(dev_priv);



	tmp = I915_READ(GUC_STATUS);

	with_intel_runtime_pm(dev_priv, wakeref) {

		u32 tmp = I915_READ(GUC_STATUS);

		u32 i;



		seq_printf(m, "\nGuC status 0x%08x:\n", tmp);

		seq_printf(m, "\tBootrom status = 0x%x\n",
@@ -2204,10 +2196,11 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data) 
		seq_printf(m, "\tMIA Core status = 0x%x\n",

			   (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);

		seq_puts(m, "\nScratch registers:\n");

	for (i = 0; i < 16; i++)

		seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));



	intel_runtime_pm_put(dev_priv, wakeref);

		for (i = 0; i < 16; i++) {

			seq_printf(m, "\t%2d: \t0x%x\n",

				   i, I915_READ(SOFT_SCRATCH(i)));

		}

	}



	return 0;

}
@@ -2680,19 +2673,14 @@ static int i915_energy_uJ(struct seq_file *m, void *data) 
	if (INTEL_GEN(dev_priv) < 6)

		return -ENODEV;



	wakeref = intel_runtime_pm_get(dev_priv);



	if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {

		intel_runtime_pm_put(dev_priv, wakeref);

	if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power))

		return -ENODEV;

	}



	units = (power & 0x1f00) >> 8;

	with_intel_runtime_pm(dev_priv, wakeref)

		power = I915_READ(MCH_SECP_NRG_STTS);

	power = (1000000 * power) >> units; /* convert to uJ */



	intel_runtime_pm_put(dev_priv, wakeref);



	power = (1000000 * power) >> units; /* convert to uJ */

	seq_printf(m, "%llu", power);



	return 0;
@@ -3275,22 +3263,20 @@ static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf, 
	struct seq_file *m = file->private_data;

	struct drm_i915_private *dev_priv = m->private;

	intel_wakeref_t wakeref;

	int ret;

	bool enable;

	int ret;



	ret = kstrtobool_from_user(ubuf, len, &enable);

	if (ret < 0)

		return ret;



	wakeref = intel_runtime_pm_get(dev_priv);



	with_intel_runtime_pm(dev_priv, wakeref) {

		if (!dev_priv->ipc_enabled && enable)

			DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");

		dev_priv->wm.distrust_bios_wm = true;

		dev_priv->ipc_enabled = enable;

		intel_enable_ipc(dev_priv);



	intel_runtime_pm_put(dev_priv, wakeref);

	}



	return len;

}
@@ -4130,17 +4116,14 @@ i915_cache_sharing_get(void *data, u64 *val) 
{

	struct drm_i915_private *dev_priv = data;

	intel_wakeref_t wakeref;

	u32 snpcr;

	u32 snpcr = 0;



	if (!(IS_GEN_RANGE(dev_priv, 6, 7)))

		return -ENODEV;



	wakeref = intel_runtime_pm_get(dev_priv);



	with_intel_runtime_pm(dev_priv, wakeref)

		snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);



	intel_runtime_pm_put(dev_priv, wakeref);



	*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;



	return 0;
@@ -4151,7 +4134,6 @@ i915_cache_sharing_set(void *data, u64 val) 
{

	struct drm_i915_private *dev_priv = data;

	intel_wakeref_t wakeref;

	u32 snpcr;



	if (!(IS_GEN_RANGE(dev_priv, 6, 7)))

		return -ENODEV;
@@ -4159,16 +4141,17 @@ i915_cache_sharing_set(void *data, u64 val) 
	if (val > 3)

		return -EINVAL;



	wakeref = intel_runtime_pm_get(dev_priv);

	DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);

	with_intel_runtime_pm(dev_priv, wakeref) {

		u32 snpcr;



		/* Update the cache sharing policy here as well */

		snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);

		snpcr &= ~GEN6_MBC_SNPCR_MASK;

	snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);

		snpcr |= val << GEN6_MBC_SNPCR_SHIFT;

		I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);

	}



	intel_runtime_pm_put(dev_priv, wakeref);

	return 0;

}
@@ -4405,20 +4388,17 @@ static int i915_sseu_status(struct seq_file *m, void *unused) 
	sseu.max_eus_per_subslice =

		RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;



	wakeref = intel_runtime_pm_get(dev_priv);



	if (IS_CHERRYVIEW(dev_priv)) {

	with_intel_runtime_pm(dev_priv, wakeref) {

		if (IS_CHERRYVIEW(dev_priv))

			cherryview_sseu_device_status(dev_priv, &sseu);

	} else if (IS_BROADWELL(dev_priv)) {

		else if (IS_BROADWELL(dev_priv))

			broadwell_sseu_device_status(dev_priv, &sseu);

	} else if (IS_GEN(dev_priv, 9)) {

		else if (IS_GEN(dev_priv, 9))

			gen9_sseu_device_status(dev_priv, &sseu);

	} else if (INTEL_GEN(dev_priv) >= 10) {

		else if (INTEL_GEN(dev_priv) >= 10)

			gen10_sseu_device_status(dev_priv, &sseu);

	}



	intel_runtime_pm_put(dev_priv, wakeref);



	i915_print_sseu_info(m, false, &sseu);



	return 0;

drivers/gpu/drm/i915/i915_gem.c

+5 −5
Original line number Diff line number Diff line
@@ -813,13 +813,13 @@ void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv) 


	i915_gem_chipset_flush(dev_priv);



	wakeref = intel_runtime_pm_get(dev_priv);

	with_intel_runtime_pm(dev_priv, wakeref) {

		spin_lock_irq(&dev_priv->uncore.lock);



		POSTING_READ_FW(RING_HEAD(RENDER_RING_BASE));



		spin_unlock_irq(&dev_priv->uncore.lock);

	intel_runtime_pm_put(dev_priv, wakeref);

	}

}



static void

drivers/gpu/drm/i915/i915_gem_gtt.c

+11 −12
Original line number Diff line number Diff line
@@ -2535,9 +2535,8 @@ static int ggtt_bind_vma(struct i915_vma *vma, 
	if (i915_gem_object_is_readonly(obj))

		pte_flags |= PTE_READ_ONLY;



	wakeref = intel_runtime_pm_get(i915);

	with_intel_runtime_pm(i915, wakeref)

		vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);

	intel_runtime_pm_put(i915, wakeref);



	vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
@@ -2556,9 +2555,8 @@ static void ggtt_unbind_vma(struct i915_vma *vma) 
	struct drm_i915_private *i915 = vma->vm->i915;

	intel_wakeref_t wakeref;



	wakeref = intel_runtime_pm_get(i915);

	with_intel_runtime_pm(i915, wakeref)

		vma->vm->clear_range(vma->vm, vma->node.start, vma->size);

	intel_runtime_pm_put(i915, wakeref);

}



static int aliasing_gtt_bind_vma(struct i915_vma *vma,
@@ -2592,9 +2590,10 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, 
	if (flags & I915_VMA_GLOBAL_BIND) {

		intel_wakeref_t wakeref;



		wakeref = intel_runtime_pm_get(i915);

		vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);

		intel_runtime_pm_put(i915, wakeref);

		with_intel_runtime_pm(i915, wakeref) {

			vma->vm->insert_entries(vma->vm, vma,

						cache_level, pte_flags);

		}

	}



	return 0;
@@ -2605,11 +2604,11 @@ static void aliasing_gtt_unbind_vma(struct i915_vma *vma) 
	struct drm_i915_private *i915 = vma->vm->i915;



	if (vma->flags & I915_VMA_GLOBAL_BIND) {

		struct i915_address_space *vm = vma->vm;

		intel_wakeref_t wakeref;



		wakeref = intel_runtime_pm_get(i915);

		vma->vm->clear_range(vma->vm, vma->node.start, vma->size);

		intel_runtime_pm_put(i915, wakeref);

		with_intel_runtime_pm(i915, wakeref)

			vm->clear_range(vm, vma->node.start, vma->size);

	}



	if (vma->flags & I915_VMA_LOCAL_BIND) {

drivers/gpu/drm/i915/i915_gem_shrinker.c

+25 −26
Original line number Diff line number Diff line
@@ -296,14 +296,14 @@ i915_gem_shrink(struct drm_i915_private *i915, 
unsigned long i915_gem_shrink_all(struct drm_i915_private *i915)

{

	intel_wakeref_t wakeref;

	unsigned long freed;

	unsigned long freed = 0;



	wakeref = intel_runtime_pm_get(i915);

	with_intel_runtime_pm(i915, wakeref) {

		freed = i915_gem_shrink(i915, -1UL, NULL,

					I915_SHRINK_BOUND |

					I915_SHRINK_UNBOUND |

					I915_SHRINK_ACTIVE);

	intel_runtime_pm_put(i915, wakeref);

	}



	return freed;

}
@@ -376,14 +376,14 @@ i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) 
	if (sc->nr_scanned < sc->nr_to_scan && current_is_kswapd()) {

		intel_wakeref_t wakeref;



		wakeref = intel_runtime_pm_get(i915);

		with_intel_runtime_pm(i915, wakeref) {

			freed += i915_gem_shrink(i915,

						 sc->nr_to_scan - sc->nr_scanned,

						 &sc->nr_scanned,

						 I915_SHRINK_ACTIVE |

						 I915_SHRINK_BOUND |

						 I915_SHRINK_UNBOUND);

		intel_runtime_pm_put(i915, wakeref);

		}

	}



	shrinker_unlock(i915, unlock);
@@ -400,11 +400,11 @@ i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) 
	unsigned long unevictable, bound, unbound, freed_pages;

	intel_wakeref_t wakeref;



	wakeref = intel_runtime_pm_get(i915);

	freed_pages = i915_gem_shrink(i915, -1UL, NULL,

	freed_pages = 0;

	with_intel_runtime_pm(i915, wakeref)

		freed_pages += i915_gem_shrink(i915, -1UL, NULL,

					       I915_SHRINK_BOUND |

					       I915_SHRINK_UNBOUND);

	intel_runtime_pm_put(i915, wakeref);



	/* Because we may be allocating inside our own driver, we cannot

	 * assert that there are no objects with pinned pages that are not
@@ -454,12 +454,11 @@ i915_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr 
				   MAX_SCHEDULE_TIMEOUT))

		goto out;



	wakeref = intel_runtime_pm_get(i915);

	with_intel_runtime_pm(i915, wakeref)

		freed_pages += i915_gem_shrink(i915, -1UL, NULL,

					       I915_SHRINK_BOUND |

					       I915_SHRINK_UNBOUND |

					       I915_SHRINK_VMAPS);

	intel_runtime_pm_put(i915, wakeref);



	/* We also want to clear any cached iomaps as they wrap vmap */

	list_for_each_entry_safe(vma, next,

drivers/gpu/drm/i915/i915_pmu.c

+2 −5
Original line number Diff line number Diff line
@@ -230,14 +230,11 @@ frequency_sample(struct drm_i915_private *dev_priv, unsigned int period_ns) 


		val = dev_priv->gt_pm.rps.cur_freq;

		if (dev_priv->gt.awake) {

			intel_wakeref_t wakeref =

				intel_runtime_pm_get_if_in_use(dev_priv);

			intel_wakeref_t wakeref;



			if (wakeref) {

			with_intel_runtime_pm_if_in_use(dev_priv, wakeref)

				val = intel_get_cagf(dev_priv,

						     I915_READ_NOTRACE(GEN6_RPSTAT1));

				intel_runtime_pm_put(dev_priv, wakeref);

			}

		}



		add_sample_mult(&dev_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],

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