Commit d41bd8f3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "The typical collection of minor bug fixes in clk drivers. We don't
  have anything in the core framework here, just driver fixes.

  There's a boot fix for Samsung devices and a safety measure for qoriq
  to prevent CPUs from running too fast. There's also a fix for i.MX6Q
  to properly handle audio clock rates. We also have some "that's
  obviously wrong" fixes like bad NULL pointer checks in the MPP driver
  and a poor usage of __pa in the xgene clk driver that are fixed here"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: mmp: pxa910: fix return value check in pxa910_clk_init()
  clk: mmp: pxa168: fix return value check in pxa168_clk_init()
  clk: mmp: mmp2: fix return value check in mmp2_clk_init()
  clk: qoriq: Don't allow CPU clocks higher than starting value
  clk: imx: fix integer overflow in AV PLL round rate
  clk: xgene: Don't call __pa on ioremaped address
  clk/samsung: Use CLK_OF_DECLARE_DRIVER initialization method for CLKOUT
  clk: rockchip: don't return NULL when failing to register ddrclk branch
parents 86e4ee76 10f2bfb0

drivers/clk/clk-qoriq.c

+8 −5
Original line number Diff line number Diff line
@@ -700,6 +700,7 @@ static struct clk * __init create_mux_common(struct clockgen *cg, 
					     struct mux_hwclock *hwc,

					     const struct clk_ops *ops,

					     unsigned long min_rate,

					     unsigned long max_rate,

					     unsigned long pct80_rate,

					     const char *fmt, int idx)

{
@@ -728,6 +729,8 @@ static struct clk * __init create_mux_common(struct clockgen *cg, 
			continue;

		if (rate < min_rate)

			continue;

		if (rate > max_rate)

			continue;



		parent_names[j] = div->name;

		hwc->parent_to_clksel[j] = i;
@@ -759,7 +762,7 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) 
	struct mux_hwclock *hwc;

	const struct clockgen_pll_div *div;

	unsigned long plat_rate, min_rate;

	u64 pct80_rate;

	u64 max_rate, pct80_rate;

	u32 clksel;



	hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
@@ -787,8 +790,8 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) 
		return NULL;

	}



	pct80_rate = clk_get_rate(div->clk);

	pct80_rate *= 8;

	max_rate = clk_get_rate(div->clk);

	pct80_rate = max_rate * 8;

	do_div(pct80_rate, 10);



	plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
@@ -798,7 +801,7 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) 
	else

		min_rate = plat_rate / 2;



	return create_mux_common(cg, hwc, &cmux_ops, min_rate,

	return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,

				 pct80_rate, "cg-cmux%d", idx);

}
@@ -813,7 +816,7 @@ static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) 
	hwc->reg = cg->regs + 0x20 * idx + 0x10;

	hwc->info = cg->info.hwaccel[idx];



	return create_mux_common(cg, hwc, &hwaccel_ops, 0, 0,

	return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,

				 "cg-hwaccel%d", idx);

}

drivers/clk/clk-xgene.c

+4 −6
Original line number Diff line number Diff line
@@ -463,22 +463,20 @@ static int xgene_clk_enable(struct clk_hw *hw) 
	struct xgene_clk *pclk = to_xgene_clk(hw);

	unsigned long flags = 0;

	u32 data;

	phys_addr_t reg;



	if (pclk->lock)

		spin_lock_irqsave(pclk->lock, flags);



	if (pclk->param.csr_reg != NULL) {

		pr_debug("%s clock enabled\n", clk_hw_get_name(hw));

		reg = __pa(pclk->param.csr_reg);

		/* First enable the clock */

		data = xgene_clk_read(pclk->param.csr_reg +

					pclk->param.reg_clk_offset);

		data |= pclk->param.reg_clk_mask;

		xgene_clk_write(data, pclk->param.csr_reg +

					pclk->param.reg_clk_offset);

		pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",

			clk_hw_get_name(hw), &reg,

		pr_debug("%s clk offset 0x%08X mask 0x%08X value 0x%08X\n",

			clk_hw_get_name(hw),

			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,

			data);
@@ -488,8 +486,8 @@ static int xgene_clk_enable(struct clk_hw *hw) 
		data &= ~pclk->param.reg_csr_mask;

		xgene_clk_write(data, pclk->param.csr_reg +

					pclk->param.reg_csr_offset);

		pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",

			clk_hw_get_name(hw), &reg,

		pr_debug("%s csr offset 0x%08X mask 0x%08X value 0x%08X\n",

			clk_hw_get_name(hw),

			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,

			data);

	}

drivers/clk/imx/clk-pllv3.c

+6 −2
Original line number Diff line number Diff line
@@ -223,7 +223,7 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, 
	temp64 *= mfn;

	do_div(temp64, mfd);



	return (parent_rate * div) + (u32)temp64;

	return parent_rate * div + (unsigned long)temp64;

}



static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -247,7 +247,11 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, 
	do_div(temp64, parent_rate);

	mfn = temp64;



	return parent_rate * div + parent_rate * mfn / mfd;

	temp64 = (u64)parent_rate;

	temp64 *= mfn;

	do_div(temp64, mfd);



	return parent_rate * div + (unsigned long)temp64;

}



static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/mmp/clk-of-mmp2.c

+1 −1
Original line number Diff line number Diff line
@@ -313,7 +313,7 @@ static void __init mmp2_clk_init(struct device_node *np) 
	}



	pxa_unit->apmu_base = of_iomap(np, 1);

	if (!pxa_unit->mpmu_base) {

	if (!pxa_unit->apmu_base) {

		pr_err("failed to map apmu registers\n");

		return;

	}

drivers/clk/mmp/clk-of-pxa168.c

+1 −1
Original line number Diff line number Diff line
@@ -262,7 +262,7 @@ static void __init pxa168_clk_init(struct device_node *np) 
	}



	pxa_unit->apmu_base = of_iomap(np, 1);

	if (!pxa_unit->mpmu_base) {

	if (!pxa_unit->apmu_base) {

		pr_err("failed to map apmu registers\n");

		return;

	}

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