Commit d4070ff7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2015-09-11' of git://anongit.freedesktop.org/drm-intel into drm-next 

- initialize backlight from VBT as fallback (Jani)
- hpd A support from Ville
- various atomic polish all over (mostly from Maarten)
- first parts of virtualize gpu guest support on bdw from
  Zhiyuan Lv
- GuC fixes from Alex
- polish for the chv clocks code (Ville)
- various things all over, as usual

* tag 'drm-intel-next-2015-09-11' of git://anongit.freedesktop.org/drm-intel: (145 commits)
  drm/i915: Update DRIVER_DATE to 20150911
  drm/i915: Remove one very outdated comment
  drm/i915: Use crtc->state for duplication.
  drm/i915: Do not handle a null plane state.
  drm/i915: Remove legacy plane updates for cursor and sprite planes.
  drm/i915: Use atomic state when changing cursor visibility.
  drm/i915: Use the atomic state in intel_update_primary_planes.
  drm/i915: Use the plane state in intel_crtc_info.
  drm/i915: Use atomic plane state in the primary plane update.
  drm/i915: add attached connector to hdmi container
  drm/i915: don't hard code vlv backlight frequency if unset
  drm/i915: initialize backlight max from VBT
  drm/i915: use pch backlight override on hsw too
  drm/i915/bxt: Clean up bxt_init_clock_gating
  drm/i915: Fix cmdparser STORE/LOAD command descriptors
  drm/i915: Dump pfit state as hex
  drm/i915: access the PP_ON_DELAYS/PP_OFF_DELAYS regs only pre GEN5
  drm/i915: access the PP_CONTROL reg only pre GEN5
  drm/i915: Refactor common ringbuffer allocation code
  drm/i915: use the yesno helper for logging
  ...
parents 2d4df13c fd1ee4cc

Documentation/DocBook/drm.tmpl

+14 −0
Original line number Diff line number Diff line
@@ -4237,6 +4237,20 @@ int num_ioctls;</synopsis> 
!Idrivers/gpu/drm/i915/i915_gem_shrinker.c

      </sect2>

    </sect1>

    <sect1>

      <title>GuC-based Command Submission</title>

      <sect2>

        <title>GuC</title>

!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC-specific firmware loader

!Idrivers/gpu/drm/i915/intel_guc_loader.c

      </sect2>

      <sect2>

        <title>GuC Client</title>

!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC-based command submissison

!Idrivers/gpu/drm/i915/i915_guc_submission.c

      </sect2>

    </sect1>



    <sect1>

      <title> Tracing </title>

      <para>

drivers/gpu/drm/i915/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -40,6 +40,10 @@ i915-y += i915_cmd_parser.o \ 
	  intel_ringbuffer.o \

	  intel_uncore.o



# general-purpose microcontroller (GuC) support

i915-y += intel_guc_loader.o \

	  i915_guc_submission.o



# autogenerated null render state

i915-y += intel_renderstate_gen6.o \

	  intel_renderstate_gen7.o \

drivers/gpu/drm/i915/i915_cmd_parser.c

+7 −6
Original line number Diff line number Diff line
@@ -124,14 +124,14 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = { 
	CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),

	CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,

	      .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 }    ),

	CMD(  MI_STORE_REGISTER_MEM(1),         SMI,   !F,  0xFF,   W | B,

	CMD(  MI_STORE_REGISTER_MEM,            SMI,    F,  3,     W | B,

	      .reg = { .offset = 1, .mask = 0x007FFFFC },

	      .bits = {{

			.offset = 0,

			.mask = MI_GLOBAL_GTT,

			.expected = 0,

	      }},						       ),

	CMD(  MI_LOAD_REGISTER_MEM(1),             SMI,   !F,  0xFF,   W | B,

	CMD(  MI_LOAD_REGISTER_MEM,             SMI,    F,  3,     W | B,

	      .reg = { .offset = 1, .mask = 0x007FFFFC },

	      .bits = {{

			.offset = 0,
@@ -1021,7 +1021,7 @@ static bool check_cmd(const struct intel_engine_cs *ring, 
			 * only MI_LOAD_REGISTER_IMM commands.

			 */

			if (reg_addr == OACONTROL) {

				if (desc->cmd.value == MI_LOAD_REGISTER_MEM(1)) {

				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {

					DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");

					return false;

				}
@@ -1035,7 +1035,7 @@ static bool check_cmd(const struct intel_engine_cs *ring, 
			 * allowed mask/value pair given in the whitelist entry.

			 */

			if (reg->mask) {

				if (desc->cmd.value == MI_LOAD_REGISTER_MEM(1)) {

				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {

					DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",

							 reg_addr);

					return false;
@@ -1213,6 +1213,7 @@ int i915_cmd_parser_get_version(void) 
	 * 2. Allow access to the MI_PREDICATE_SRC0 and

	 *    MI_PREDICATE_SRC1 registers.

	 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.

	 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.

	 */

	return 3;

	return 4;

}

drivers/gpu/drm/i915/i915_debugfs.c

+168 −28
Original line number Diff line number Diff line
@@ -46,11 +46,6 @@ enum { 
	PINNED_LIST,

};



static const char *yesno(int v)

{

	return v ? "yes" : "no";

}



/* As the drm_debugfs_init() routines are called before dev->dev_private is

 * allocated we need to hook into the minor for release. */

static int
@@ -1387,17 +1382,16 @@ static int ironlake_drpc_info(struct seq_file *m) 
	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);



	seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?

		   "yes" : "no");

	seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));

	seq_printf(m, "Boost freq: %d\n",

		   (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>

		   MEMMODE_BOOST_FREQ_SHIFT);

	seq_printf(m, "HW control enabled: %s\n",

		   rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");

		   yesno(rgvmodectl & MEMMODE_HWIDLE_EN));

	seq_printf(m, "SW control enabled: %s\n",

		   rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");

		   yesno(rgvmodectl & MEMMODE_SWMODE_EN));

	seq_printf(m, "Gated voltage change: %s\n",

		   rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");

		   yesno(rgvmodectl & MEMMODE_RCLK_GATE));

	seq_printf(m, "Starting frequency: P%d\n",

		   (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);

	seq_printf(m, "Max P-state: P%d\n",
@@ -1406,7 +1400,7 @@ static int ironlake_drpc_info(struct seq_file *m) 
	seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));

	seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));

	seq_printf(m, "Render standby enabled: %s\n",

		   (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");

		   yesno(!(rstdbyctl & RCX_SW_EXIT)));

	seq_puts(m, "Current RS state: ");

	switch (rstdbyctl & RSX_STATUS_MASK) {

	case RSX_STATUS_ON:
@@ -1995,7 +1989,7 @@ static void i915_dump_lrc_obj(struct seq_file *m, 
		return;

	}



	page = i915_gem_object_get_page(ctx_obj, 1);

	page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);

	if (!WARN_ON(page == NULL)) {

		reg_state = kmap_atomic(page);
@@ -2250,7 +2244,6 @@ static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_engine_cs *ring;

	struct drm_file *file;

	int i;



	if (INTEL_INFO(dev)->gen == 6)
@@ -2273,13 +2266,6 @@ static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) 
		ppgtt->debug_dump(ppgtt, m);

	}



	list_for_each_entry_reverse(file, &dev->filelist, lhead) {

		struct drm_i915_file_private *file_priv = file->driver_priv;



		seq_printf(m, "proc: %s\n",

			   get_pid_task(file->pid, PIDTYPE_PID)->comm);

		idr_for_each(&file_priv->context_idr, per_file_ctx, m);

	}

	seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));

}
@@ -2288,6 +2274,7 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) 
	struct drm_info_node *node = m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_file *file;



	int ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)
@@ -2299,6 +2286,15 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) 
	else if (INTEL_INFO(dev)->gen >= 6)

		gen6_ppgtt_info(m, dev);



	list_for_each_entry_reverse(file, &dev->filelist, lhead) {

		struct drm_i915_file_private *file_priv = file->driver_priv;



		seq_printf(m, "\nproc: %s\n",

			   get_pid_task(file->pid, PIDTYPE_PID)->comm);

		idr_for_each(&file_priv->context_idr, per_file_ctx,

			     (void *)(unsigned long)m);

	}



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);
@@ -2372,6 +2368,147 @@ static int i915_llc(struct seq_file *m, void *data) 
	return 0;

}



static int i915_guc_load_status_info(struct seq_file *m, void *data)

{

	struct drm_info_node *node = m->private;

	struct drm_i915_private *dev_priv = node->minor->dev->dev_private;

	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;

	u32 tmp, i;



	if (!HAS_GUC_UCODE(dev_priv->dev))

		return 0;



	seq_printf(m, "GuC firmware status:\n");

	seq_printf(m, "\tpath: %s\n",

		guc_fw->guc_fw_path);

	seq_printf(m, "\tfetch: %s\n",

		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));

	seq_printf(m, "\tload: %s\n",

		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));

	seq_printf(m, "\tversion wanted: %d.%d\n",

		guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);

	seq_printf(m, "\tversion found: %d.%d\n",

		guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);



	tmp = I915_READ(GUC_STATUS);



	seq_printf(m, "\nGuC status 0x%08x:\n", tmp);

	seq_printf(m, "\tBootrom status = 0x%x\n",

		(tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);

	seq_printf(m, "\tuKernel status = 0x%x\n",

		(tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);

	seq_printf(m, "\tMIA Core status = 0x%x\n",

		(tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);

	seq_puts(m, "\nScratch registers:\n");

	for (i = 0; i < 16; i++)

		seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));



	return 0;

}



static void i915_guc_client_info(struct seq_file *m,

				 struct drm_i915_private *dev_priv,

				 struct i915_guc_client *client)

{

	struct intel_engine_cs *ring;

	uint64_t tot = 0;

	uint32_t i;



	seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",

		client->priority, client->ctx_index, client->proc_desc_offset);

	seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",

		client->doorbell_id, client->doorbell_offset, client->cookie);

	seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",

		client->wq_size, client->wq_offset, client->wq_tail);



	seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);

	seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);

	seq_printf(m, "\tLast submission result: %d\n", client->retcode);



	for_each_ring(ring, dev_priv, i) {

		seq_printf(m, "\tSubmissions: %llu %s\n",

				client->submissions[i],

				ring->name);

		tot += client->submissions[i];

	}

	seq_printf(m, "\tTotal: %llu\n", tot);

}



static int i915_guc_info(struct seq_file *m, void *data)

{

	struct drm_info_node *node = m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_guc guc;

	struct i915_guc_client client = {};

	struct intel_engine_cs *ring;

	enum intel_ring_id i;

	u64 total = 0;



	if (!HAS_GUC_SCHED(dev_priv->dev))

		return 0;



	/* Take a local copy of the GuC data, so we can dump it at leisure */

	spin_lock(&dev_priv->guc.host2guc_lock);

	guc = dev_priv->guc;

	if (guc.execbuf_client) {

		spin_lock(&guc.execbuf_client->wq_lock);

		client = *guc.execbuf_client;

		spin_unlock(&guc.execbuf_client->wq_lock);

	}

	spin_unlock(&dev_priv->guc.host2guc_lock);



	seq_printf(m, "GuC total action count: %llu\n", guc.action_count);

	seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);

	seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);

	seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);

	seq_printf(m, "GuC last action error code: %d\n", guc.action_err);



	seq_printf(m, "\nGuC submissions:\n");

	for_each_ring(ring, dev_priv, i) {

		seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",

			ring->name, guc.submissions[i],

			guc.last_seqno[i], guc.last_seqno[i]);

		total += guc.submissions[i];

	}

	seq_printf(m, "\t%s: %llu\n", "Total", total);



	seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);

	i915_guc_client_info(m, dev_priv, &client);



	/* Add more as required ... */



	return 0;

}



static int i915_guc_log_dump(struct seq_file *m, void *data)

{

	struct drm_info_node *node = m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;

	u32 *log;

	int i = 0, pg;



	if (!log_obj)

		return 0;



	for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {

		log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));



		for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)

			seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",

				   *(log + i), *(log + i + 1),

				   *(log + i + 2), *(log + i + 3));



		kunmap_atomic(log);

	}



	seq_putc(m, '\n');



	return 0;

}



static int i915_edp_psr_status(struct seq_file *m, void *data)

{

	struct drm_info_node *node = m->private;
@@ -2680,11 +2817,13 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) 
	struct drm_device *dev = node->minor->dev;

	struct drm_crtc *crtc = &intel_crtc->base;

	struct intel_encoder *intel_encoder;

	struct drm_plane_state *plane_state = crtc->primary->state;

	struct drm_framebuffer *fb = plane_state->fb;



	if (crtc->primary->fb)

	if (fb)

		seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",

			   crtc->primary->fb->base.id, crtc->x, crtc->y,

			   crtc->primary->fb->width, crtc->primary->fb->height);

			   fb->base.id, plane_state->src_x >> 16,

			   plane_state->src_y >> 16, fb->width, fb->height);

	else

		seq_puts(m, "\tprimary plane disabled\n");

	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
@@ -2706,8 +2845,7 @@ static void intel_dp_info(struct seq_file *m, 
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);



	seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);

	seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :

		   "no");

	seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));

	if (intel_encoder->type == INTEL_OUTPUT_EDP)

		intel_panel_info(m, &intel_connector->panel);

}
@@ -2718,8 +2856,7 @@ static void intel_hdmi_info(struct seq_file *m, 
	struct intel_encoder *intel_encoder = intel_connector->encoder;

	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);



	seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :

		   "no");

	seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));

}



static void intel_lvds_info(struct seq_file *m,
@@ -4807,7 +4944,7 @@ static void cherryview_sseu_device_status(struct drm_device *dev, 
					  struct sseu_dev_status *stat)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	const int ss_max = 2;

	int ss_max = 2;

	int ss;

	u32 sig1[ss_max], sig2[ss_max];
@@ -5033,6 +5170,9 @@ static const struct drm_info_list i915_debugfs_list[] = { 
	{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},

	{"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},

	{"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},

	{"i915_guc_info", i915_guc_info, 0},

	{"i915_guc_load_status", i915_guc_load_status_info, 0},

	{"i915_guc_log_dump", i915_guc_log_dump, 0},

	{"i915_frequency_info", i915_frequency_info, 0},

	{"i915_hangcheck_info", i915_hangcheck_info, 0},

	{"i915_drpc_info", i915_drpc_info, 0},

drivers/gpu/drm/i915/i915_dma.c

+31 −4
Original line number Diff line number Diff line
@@ -364,12 +364,12 @@ static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_ 
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;

		/* i915 resume handler doesn't set to D0 */

		pci_set_power_state(dev->pdev, PCI_D0);

		i915_resume_legacy(dev);

		i915_resume_switcheroo(dev);

		dev->switch_power_state = DRM_SWITCH_POWER_ON;

	} else {

		pr_err("switched off\n");

		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;

		i915_suspend_legacy(dev, pmm);

		i915_suspend_switcheroo(dev, pmm);

		dev->switch_power_state = DRM_SWITCH_POWER_OFF;

	}

}
@@ -435,6 +435,11 @@ static int i915_load_modeset_init(struct drm_device *dev) 
	 * working irqs for e.g. gmbus and dp aux transfers. */

	intel_modeset_init(dev);



	/* intel_guc_ucode_init() needs the mutex to allocate GEM objects */

	mutex_lock(&dev->struct_mutex);

	intel_guc_ucode_init(dev);

	mutex_unlock(&dev->struct_mutex);



	ret = i915_gem_init(dev);

	if (ret)

		goto cleanup_irq;
@@ -476,6 +481,9 @@ cleanup_gem: 
	i915_gem_context_fini(dev);

	mutex_unlock(&dev->struct_mutex);

cleanup_irq:

	mutex_lock(&dev->struct_mutex);

	intel_guc_ucode_fini(dev);

	mutex_unlock(&dev->struct_mutex);

	drm_irq_uninstall(dev);

cleanup_gem_stolen:

	i915_gem_cleanup_stolen(dev);
@@ -791,6 +799,24 @@ static void intel_device_info_runtime_init(struct drm_device *dev) 
			 info->has_eu_pg ? "y" : "n");

}



static void intel_init_dpio(struct drm_i915_private *dev_priv)

{

	if (!IS_VALLEYVIEW(dev_priv))

		return;



	/*

	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),

	 * CHV x1 PHY (DP/HDMI D)

	 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)

	 */

	if (IS_CHERRYVIEW(dev_priv)) {

		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;

		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;

	} else {

		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;

	}

}



/**

 * i915_driver_load - setup chip and create an initial config

 * @dev: DRM device
@@ -971,8 +997,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	intel_setup_gmbus(dev);

	intel_opregion_setup(dev);



	intel_setup_bios(dev);



	i915_gem_load(dev);



	/* On the 945G/GM, the chipset reports the MSI capability on the
@@ -991,6 +1015,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 


	intel_device_info_runtime_init(dev);



	intel_init_dpio(dev_priv);



	if (INTEL_INFO(dev)->num_pipes) {

		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);

		if (ret)
@@ -1128,6 +1154,7 @@ int i915_driver_unload(struct drm_device *dev) 
	flush_workqueue(dev_priv->wq);



	mutex_lock(&dev->struct_mutex);

	intel_guc_ucode_fini(dev);

	i915_gem_cleanup_ringbuffer(dev);

	i915_gem_context_fini(dev);

	mutex_unlock(&dev->struct_mutex);

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