Commit d405e4b0 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra into tegra/soc 

From: Olof Johansson <olof@lixom.net>

SoC new development for tegra SoCs, mostly tegra30 core support.

It also includes one stray bugfix that was misapplied (should have been
in soc-drivers), but it went out to the stable branches before I noticed
so I've left it in.

* tag 'tegra-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra

:
  ARM: tegra: Demote EMC clock inconsistency BUG to WARN
  ARM: tegra: Avoid compiling cpuidle code when not configured
  ARM: tegra: cpuidle driver for tegra
  ARM: tegra: assembler code for LP3
  ARM: tegra: definitions for flow controller
  ARM: tegra: initialize basic system clocks
  ARM: tegra: enable tegra30 clock framework
  ARM: tegra: implement basic tegra30 clock framework
  ARM: tegra: add support for new clock framework features
  ARM: tegra: add support for tegra30 interrupts

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 62aa2b53 e186ad74

arch/arm/mach-tegra/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -7,12 +7,15 @@ obj-y += clock.o 
obj-y                                   += timer.o

obj-y                                   += pinmux.o

obj-y					+= fuse.o

obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o

obj-$(CONFIG_CPU_IDLE)			+= sleep.o

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= powergate.o

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-tegra20-tables.o

obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= pinmux-tegra30-tables.o

obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o

obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o

obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o

obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o

obj-$(CONFIG_TEGRA_SYSTEM_DMA)		+= dma.o

arch/arm/mach-tegra/board-dt-tegra30.c

+23 −1
Original line number Diff line number Diff line
@@ -34,16 +34,38 @@ 
#include <asm/hardware/gic.h>



#include "board.h"

#include "clock.h"



static struct of_device_id tegra_dt_match_table[] __initdata = {

	{ .compatible = "simple-bus", },

	{}

};



struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {

	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),

	{}

};



static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {

	/* name		parent		rate		enabled */

	{ "uartd",	"pll_p",	408000000,	true },

	{ NULL,		NULL,		0,		0},

};



static void __init tegra30_dt_init(void)

{

	tegra_clk_init_from_table(tegra_dt_clk_init_table);



	of_platform_populate(NULL, tegra_dt_match_table,

				NULL, NULL);

				tegra30_auxdata_lookup, NULL);

}



static const char *tegra30_dt_board_compat[] = {

arch/arm/mach-tegra/clock.c

+22 −0
Original line number Diff line number Diff line
@@ -399,6 +399,28 @@ void tegra_periph_reset_assert(struct clk *c) 
}

EXPORT_SYMBOL(tegra_periph_reset_assert);



/* Several extended clock configuration bits (e.g., clock routing, clock

 * phase control) are included in PLL and peripheral clock source

 * registers. */

int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)

{

	int ret = 0;

	unsigned long flags;



	spin_lock_irqsave(&c->spinlock, flags);



	if (!c->ops || !c->ops->clk_cfg_ex) {

		ret = -ENOSYS;

		goto out;

	}

	ret = c->ops->clk_cfg_ex(c, p, setting);



out:

	spin_unlock_irqrestore(&c->spinlock, flags);



	return ret;

}



#ifdef CONFIG_DEBUG_FS



static int __clk_lock_all_spinlocks(void)

arch/arm/mach-tegra/clock.h

+15 −0
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ 
#include <linux/list.h>

#include <linux/spinlock.h>



#include <mach/clk.h>



#define DIV_BUS			(1 << 0)

#define DIV_U71			(1 << 1)

#define DIV_U71_FIXED		(1 << 2)
@@ -39,7 +41,16 @@ 
#define PERIPH_MANUAL_RESET	(1 << 12)

#define PLL_ALT_MISC_REG	(1 << 13)

#define PLLU			(1 << 14)

#define PLLX                    (1 << 15)

#define MUX_PWM                 (1 << 16)

#define MUX8                    (1 << 17)

#define DIV_U71_UART            (1 << 18)

#define MUX_CLK_OUT             (1 << 19)

#define PLLM                    (1 << 20)

#define DIV_U71_INT             (1 << 21)

#define DIV_U71_IDLE            (1 << 22)

#define ENABLE_ON_INIT		(1 << 28)

#define PERIPH_ON_APB           (1 << 29)



struct clk;
@@ -65,6 +76,8 @@ struct clk_ops { 
	int		(*set_rate)(struct clk *, unsigned long);

	long		(*round_rate)(struct clk *, unsigned long);

	void		(*reset)(struct clk *, bool);

	int		(*clk_cfg_ex)(struct clk *,

				enum tegra_clk_ex_param, u32);

};



enum clk_state {
@@ -114,6 +127,7 @@ struct clk { 
			unsigned long			vco_max;

			const struct clk_pll_freq_table	*freq_table;

			int				lock_delay;

			unsigned long			fixed_rate;

		} pll;

		struct {

			u32				sel;
@@ -146,6 +160,7 @@ struct tegra_clk_init_table { 
};



void tegra2_init_clocks(void);

void tegra30_init_clocks(void);

void clk_init(struct clk *clk);

struct clk *tegra_get_clock_by_name(const char *name);

int clk_reparent(struct clk *c, struct clk *parent);

arch/arm/mach-tegra/common.c

+1 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ void __init tegra20_init_early(void) 
#ifdef CONFIG_ARCH_TEGRA_3x_SOC

void __init tegra30_init_early(void)

{

	tegra30_init_clocks();

	tegra_init_cache(0x441, 0x551);

}

#endif

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