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We have a use case with the da850 SATA controller where at PLL0 frequency of 456MHz (needed to properly service the LCD controller) the chip becomes unstable and the hardreset operation is ignored the first time 50% of times. The sata core driver already retries to resume the link because some controllers ignore writes to the SControl register, but just retrying the resume operation doesn't work - we need to issue he phy/wake reset again to make it work. Reimplement ahci_hardreset() in the driver and poke the controller a couple times before really giving up. Signed-off-by:Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by:
Tejun Heo <tj@kernel.org> Signed-off-by:
Sekhar Nori <nsekhar@ti.com>
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