Commit d39fc265 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-qcom' into clk-next 

 - Enable CPU clks on Qualcomm MSM8996 SoCs

* clk-qcom:
  clk: qcom: Add CPU clock driver for msm8996
  dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996
  soc: qcom: Separate kryo l2 accessors from PMU driver
  clk: qcom: Fix return value check in apss_ipq6018_probe()
parents 12ef3933 03e342dc

Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml

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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,kryocc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm clock controller for MSM8996 CPUs



maintainers:

  - Loic Poulain <loic.poulain@linaro.org>



description: |

  Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster

  and clock 1 is for Perf cluster.



properties:

  compatible:

    enum:

      - qcom,msm8996-apcc



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  clocks:

    items:

      - description: Primary PLL clock for power cluster (little)

      - description: Primary PLL clock for perf cluster (big)

      - description: Alternate PLL clock for power cluster (little)

      - description: Alternate PLL clock for perf cluster (big)



  clock-names:

    items:

      - const: pwrcl_pll

      - const: perfcl_pll

      - const: pwrcl_alt_pll

      - const: perfcl_alt_pll



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  # Example for msm8996

  - |

    kryocc: clock-controller@6400000 {

        compatible = "qcom,msm8996-apcc";

        reg = <0x6400000 0x90000>;

        #clock-cells = <1>;

  };

...

drivers/clk/qcom/Kconfig

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@@ -37,6 +37,15 @@ config QCOM_CLK_APCS_MSM8916 
	  Say Y if you want to support CPU frequency scaling on devices

	  such as msm8916.



config QCOM_CLK_APCC_MSM8996

	tristate "MSM8996 CPU Clock Controller"

	select QCOM_KRYO_L2_ACCESSORS

	depends on ARM64

	help

	  Support for the CPU clock controller on msm8996 devices.

	  Say Y if you want to support CPU clock scaling using CPUfreq

	  drivers for dyanmic power management.



config QCOM_CLK_RPM

	tristate "RPM based Clock Controller"

	depends on MFD_QCOM_RPM

drivers/clk/qcom/Makefile

+1 −0
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@@ -44,6 +44,7 @@ obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o 
obj-$(CONFIG_MSM_MMCC_8998) += mmcc-msm8998.o

obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o

obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o

obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o

obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o

obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o

obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o

drivers/clk/qcom/apss-ipq6018.c

+2 −2
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@@ -87,8 +87,8 @@ static int apss_ipq6018_probe(struct platform_device *pdev) 
	struct regmap *regmap;



	regmap = dev_get_regmap(pdev->dev.parent, NULL);

	if (IS_ERR(regmap))

		return PTR_ERR(regmap);

	if (!regmap)

		return -ENODEV;



	return qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);

}

drivers/clk/qcom/clk-alpha-pll.h

+6 −0
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@@ -47,6 +47,12 @@ struct pll_vco { 
	u32 val;

};



#define VCO(a, b, c) { \

	.val = a,\

	.min_freq = b,\

	.max_freq = c,\

}



/**

 * struct clk_alpha_pll - phase locked loop (PLL)

 * @offset: base address of registers

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