Commit d3991572 authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Thomas Bogendoerfer
Browse files

MIPS: cleanup fixup_bigphys_addr handling 



fixup_bigphys_addr is only provided by the alchemy platform.  Remove
all the stubs, and ensure we only call it if it is actually implemented.

Also don't bother implementing io_remap_pfn_range if we don't have to,
and move the remaining implementation to alchemy platform code.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent b604d497

arch/mips/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -92,6 +92,9 @@ config MIPS 
	select SYSCTL_EXCEPTION_TRACE

	select VIRT_TO_BUS



config MIPS_FIXUP_BIGPHYS_ADDR

	bool



menu "Machine selection"



choice
@@ -157,6 +160,7 @@ config MIPS_ALCHEMY 
	select CSRC_R4K

	select IRQ_MIPS_CPU

	select DMA_MAYBE_COHERENT	# Au1000,1500,1100 aren't, rest is

	select MIPS_FIXUP_BIGPHYS_ADDR if PCI

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_APM_EMULATION

arch/mips/alchemy/common/setup.c

+12 −4
Original line number Diff line number Diff line
@@ -72,9 +72,9 @@ void __init plat_mem_setup(void) 
	iomem_resource.end = IOMEM_RESOURCE_END;

}



#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)

#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR

/* This routine should be valid for all Au1x based boards */

phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)

phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)

{

	unsigned long start = ALCHEMY_PCI_MEMWIN_START;

	unsigned long end = ALCHEMY_PCI_MEMWIN_END;
@@ -90,5 +90,13 @@ phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) 
	/* default nop */

	return phys_addr;

}

EXPORT_SYMBOL(__fixup_bigphys_addr);

#endif
 


int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,

		unsigned long pfn, unsigned long size, pgprot_t prot)

{

	phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);



	return remap_pfn_range(vma, vaddr, phys_addr >> PAGE_SHIFT, size, prot);

}

EXPORT_SYMBOL(io_remap_pfn_range);

#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */

arch/mips/include/asm/mach-au1x00/ioremap.h

deleted100644 → 0
+0 −38
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 *	include/asm-mips/mach-au1x00/ioremap.h

 */

#ifndef __ASM_MACH_AU1X00_IOREMAP_H

#define __ASM_MACH_AU1X00_IOREMAP_H



#include <linux/types.h>



#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)

extern phys_addr_t __fixup_bigphys_addr(phys_addr_t, phys_addr_t);

#else

static inline phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)

{

	return phys_addr;

}

#endif



/*

 * Allow physical addresses to be fixed up to help 36-bit peripherals.

 */

static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)

{

	return __fixup_bigphys_addr(phys_addr, size);

}



static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,

	unsigned long flags)

{

	return NULL;

}



static inline int plat_iounmap(const volatile void __iomem *addr)

{

	return 0;

}



#endif /* __ASM_MACH_AU1X00_IOREMAP_H */

arch/mips/include/asm/mach-bcm63xx/ioremap.h

+0 −5
Original line number Diff line number Diff line
@@ -4,11 +4,6 @@ 


#include <bcm63xx_cpu.h>



static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)

{

	return phys_addr;

}



static inline int is_bcm63xx_internal_registers(phys_addr_t offset)

{

	switch (bcm63xx_get_cpu_id()) {

arch/mips/include/asm/mach-bmips/ioremap.h

+0 −5
Original line number Diff line number Diff line
@@ -4,11 +4,6 @@ 


#include <linux/types.h>



static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)

{

	return phys_addr;

}



static inline int is_bmips_internal_registers(phys_addr_t offset)

{

	if (offset >= 0xfff80000)

CRA Git | Maintained and supported by SUSTech CRA and CCSE