sh: Hook up remaining IRQ sources for R7780MP FPGA.

	UNUSED = 0,

	/* board specific interrupt sources */

	AX88796,          /* Ethernet controller */

	CF,		/* Compact Flash */

	TP,		/* Touch panel */

	SCIF1,		/* FPGA SCIF1 */

	SCIF0,		/* FPGA SCIF0 */

	SMBUS,		/* SMBUS */

	RTC,		/* RTC Alarm */

	AX88796,	/* Ethernet controller */

	PSW,		/* Push Switch */

	EXT1,             /* EXT1n IRQ */

	EXT4,             /* EXT4n IRQ */

	/* external bus connector */

	EXT1, EXT2, EXT4, EXT5, EXT6,

};

static struct intc_vect vectors[] __initdata = {

	INTC_IRQ(CF, IRQ_CF),

	INTC_IRQ(PSW, IRQ_PSW),

	INTC_IRQ(TP, IRQ_TP),

	INTC_IRQ(SCIF1, IRQ_SCIF1),

	INTC_IRQ(SCIF0, IRQ_SCIF0),

	INTC_IRQ(SMBUS, IRQ_SMBUS),

	INTC_IRQ(RTC, IRQ_RTC),

	INTC_IRQ(AX88796, IRQ_AX88796),

	INTC_IRQ(EXT1, IRQ_EXT1),

	INTC_IRQ(EXT4, IRQ_EXT4),

	INTC_IRQ(PSW, IRQ_PSW),

	INTC_IRQ(EXT1, IRQ_EXT1), INTC_IRQ(EXT2, IRQ_EXT2),

	INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5),

	INTC_IRQ(EXT6, IRQ_EXT6),

};

static struct intc_mask_reg mask_registers[] __initdata = {

	{ 0xa4000000, 0, 16, /* IRLMSK */

	  { 0, 0, 0, 0, CF, 0, 0, 0,

	    0, 0, 0, EXT4, 0, EXT1, PSW, AX88796 } },

	  { SCIF0, SCIF1, RTC, 0, CF, 0, TP, SMBUS,

	    0, EXT6, EXT5, EXT4, EXT2, EXT1, PSW, AX88796 } },

};

static unsigned char irl2irq[HL_NR_IRL] __initdata = {

	0, IRQ_CF, 0, 0,

	0, 0, 0, 0,

	0, IRQ_EXT4, 0, IRQ_EXT1,

	0, IRQ_CF, IRQ_TP, IRQ_SCIF1,

	IRQ_SCIF0, IRQ_SMBUS, IRQ_RTC, IRQ_EXT6,

	IRQ_EXT5, IRQ_EXT4, IRQ_EXT2, IRQ_EXT1,

	0, IRQ_AX88796, IRQ_PSW,

};

#define PA_SCSPTR1      (PA_BCR+0x0524) /* SCIF1 Serial Port control */

#define PA_SCLSR1       (PA_BCR+0x0528) /* SCIF1 Line Status control */

#define PA_SCRER1       (PA_BCR+0x052c) /* SCIF1 Serial Error control */

#define PA_ICCR         (PA_BCR+0x0600) /* Serial control */

#define PA_SAR          (PA_BCR+0x0602) /* Serial Slave control */

#define PA_MDR          (PA_BCR+0x0604) /* Serial Mode control */

#define PA_ADR1         (PA_BCR+0x0606) /* Serial Address1 control */

#define PA_DAR1         (PA_BCR+0x0646) /* Serial Data1 control */

#define PA_SMCR         (PA_BCR+0x0600) /* 2-wire Serial control */

#define PA_SMSMADR      (PA_BCR+0x0602) /* 2-wire Serial Slave control */

#define PA_SMMR         (PA_BCR+0x0604) /* 2-wire Serial Mode control */

#define PA_SMSADR1      (PA_BCR+0x0606) /* 2-wire Serial Address1 control */

#define PA_SMTRDR1      (PA_BCR+0x0646) /* 2-wire Serial Data1 control */

#define PA_VERREG       (PA_BCR+0x0700) /* FPGA Version Register */

#define PA_POFF         (PA_BCR+0x0800) /* System Power Off control */

#define PA_PMR          (PA_BCR+0x0900) /*  */

#define PA_SCFCR	(PA_BCR+0x040c)	/* SCIF FIFO control */

#define PA_SCFDR	(PA_BCR+0x040e)	/* SCIF FIFO data control */

#define PA_SCLSR	(PA_BCR+0x0412)	/* SCIF Line Status control */

#define PA_ICCR		(PA_BCR+0x0500)	/* Serial control */

#define PA_SAR		(PA_BCR+0x0502)	/* Serial Slave control */

#define PA_MDR		(PA_BCR+0x0504)	/* Serial Mode control */

#define PA_ADR1		(PA_BCR+0x0506)	/* Serial Address1 control */

#define PA_DAR1		(PA_BCR+0x0546)	/* Serial Data1 control */

#define PA_SMCR		(PA_BCR+0x0500)	/* 2-wire Serial control */

#define PA_SMSMADR	(PA_BCR+0x0502)	/* 2-wire Serial Slave control */

#define PA_SMMR		(PA_BCR+0x0504)	/* 2-wire Serial Mode control */

#define PA_SMSADR1	(PA_BCR+0x0506)	/* 2-wire Serial Address1 control */

#define PA_SMTRDR1	(PA_BCR+0x0546)	/* 2-wire Serial Data1 control */

#define PA_VERREG	(PA_BCR+0x0600)	/* FPGA Version Register */

#define PA_AX88796L	0xa5800400	/* AX88796L Area */

#define IRQ_TP			(HL_FPGA_IRQ_BASE + 12)

#define IRQ_RTC			(HL_FPGA_IRQ_BASE + 13)

#define IRQ_TH_ALERT		(HL_FPGA_IRQ_BASE + 14)

#define IRQ_SCIF0		(HL_FPGA_IRQ_BASE + 15)

#define IRQ_SCIF1		(HL_FPGA_IRQ_BASE + 16)

unsigned char *highlander_init_irq_r7780mp(void);

unsigned char *highlander_init_irq_r7780rp(void);