Commit d38c3ac7 authored by Guchun Chen's avatar Guchun Chen Committed by Alex Deucher
Browse files

drm/amdgpu: toggle DF-Cstate when accessing UMC ras error related registers 



On arcturus, DF-Cstate needs to be toggled off/on
before and after accessing UMC error counter and
error address registers, otherwise, clearing such
registers may fail.

Signed-off-by: default avatarGuchun Chen <guchun.chen@amd.com>
Reviewed-by: default avatarJohn Clements <John.Clements@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1b3460a8

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

+16 −0
Original line number Diff line number Diff line
@@ -186,6 +186,10 @@ static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev, 
	if (rsmu_umc_index_state)

		umc_v6_1_disable_umc_index_mode(adev);



	if ((adev->asic_type == CHIP_ARCTURUS) &&

		amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))

		DRM_WARN("Fail to disable DF-Cstate.\n");



	LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {

		umc_reg_offset = get_umc_6_reg_offset(adev,

						      umc_inst,
@@ -199,6 +203,10 @@ static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev, 
							  &(err_data->ue_count));

	}



	if ((adev->asic_type == CHIP_ARCTURUS) &&

		amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))

		DRM_WARN("Fail to enable DF-Cstate\n");



	if (rsmu_umc_index_state)

		umc_v6_1_enable_umc_index_mode(adev);

}
@@ -288,6 +296,10 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, 
	if (rsmu_umc_index_state)

		umc_v6_1_disable_umc_index_mode(adev);



	if ((adev->asic_type == CHIP_ARCTURUS) &&

		amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))

		DRM_WARN("Fail to disable DF-Cstate.\n");



	LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {

		umc_reg_offset = get_umc_6_reg_offset(adev,

						      umc_inst,
@@ -300,6 +312,10 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, 
					     umc_inst);

	}



	if ((adev->asic_type == CHIP_ARCTURUS) &&

		amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))

		DRM_WARN("Fail to enable DF-Cstate\n");



	if (rsmu_umc_index_state)

		umc_v6_1_enable_umc_index_mode(adev);

}

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