Commit d3736340 authored by Alan Cox's avatar Alan Cox Committed by Linus Torvalds
Browse files

nvidiafb/rivafb: switch to pci_get refcounting 



Switch to pci_get refcounting APIs

[adaplas]
Fix a long-standing bug where the return value of
pci_find_slot()/pci_get_bus_and_slot() is ignored.

Signed-off-by: default avatarAlan Cox <alan@redhat.com>
Signed-off-by: default avatarAntonino Daplas <adaplas@gmail.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent dbe7e429

drivers/video/nvidia/nv_hw.c

+9 −6
Original line number Diff line number Diff line
@@ -686,7 +686,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, 


	if ((par->Chipset & 0x0FF0) == 0x01A0) {

		unsigned int uMClkPostDiv;

		dev = pci_find_slot(0, 3);

		dev = pci_get_bus_and_slot(0, 3);

		pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);

		uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
@@ -694,11 +694,11 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, 
			uMClkPostDiv = 4;

		MClk = 400000 / uMClkPostDiv;

	} else {

		dev = pci_find_slot(0, 5);

		dev = pci_get_bus_and_slot(0, 5);

		pci_read_config_dword(dev, 0x4c, &MClk);

		MClk /= 1000;

	}



	pci_dev_put(dev);

	pll = NV_RD32(par->PRAMDAC0, 0x0500);

	M = (pll >> 0) & 0xFF;

	N = (pll >> 8) & 0xFF;
@@ -707,19 +707,21 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, 
	sim_data.pix_bpp = (char)pixelDepth;

	sim_data.enable_video = 0;

	sim_data.enable_mp = 0;

	pci_find_slot(0, 1);

	dev = pci_get_bus_and_slot(0, 1);

	pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);

	pci_dev_put(dev);

	sim_data.memory_type = (sim_data.memory_type >> 12) & 1;

	sim_data.memory_width = 64;



	dev = pci_find_slot(0, 3);

	dev = pci_get_bus_and_slot(0, 3);

	pci_read_config_dword(dev, 0, &memctrl);

	pci_dev_put(dev);

	memctrl >>= 16;



	if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {

		int dimm[3];



		pci_find_slot(0, 2);

		dev = pci_get_bus_and_slot(0, 2);

		pci_read_config_dword(dev, 0x40, &dimm[0]);

		dimm[0] = (dimm[0] >> 8) & 0x4f;

		pci_read_config_dword(dev, 0x44, &dimm[1]);
@@ -731,6 +733,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, 
			printk("nvidiafb: your nForce DIMMs are not arranged "

			       "in optimal banks!\n");

		}

		pci_dev_put(dev);

	}



	sim_data.mem_latency = 3;

drivers/video/nvidia/nv_setup.c

+2 −1
Original line number Diff line number Diff line
@@ -261,7 +261,7 @@ static void nv10GetConfig(struct nvidia_par *par) 
	}

#endif



	dev = pci_find_slot(0, 1);

	dev = pci_get_bus_and_slot(0, 1);

	if ((par->Chipset & 0xffff) == 0x01a0) {

		int amt = 0;
@@ -276,6 +276,7 @@ static void nv10GetConfig(struct nvidia_par *par) 
		par->RamAmountKBytes =

		    (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;

	}

	pci_dev_put(dev);



	par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?

	    14318 : 13500;

drivers/video/riva/nv_driver.c

+4 −2
Original line number Diff line number Diff line
@@ -231,12 +231,14 @@ unsigned long riva_get_memlen(struct riva_par *par) 
	case NV_ARCH_30:

		if(chipset == NV_CHIP_IGEFORCE2) {



			dev = pci_find_slot(0, 1);

			dev = pci_get_bus_and_slot(0, 1);

			pci_read_config_dword(dev, 0x7C, &amt);

			pci_dev_put(dev);

			memlen = (((amt >> 6) & 31) + 1) * 1024;

		} else if (chipset == NV_CHIP_0x01F0) {

			dev = pci_find_slot(0, 1);

			dev = pci_get_bus_and_slot(0, 1);

			pci_read_config_dword(dev, 0x84, &amt);

			pci_dev_put(dev);

			memlen = (((amt >> 4) & 127) + 1) * 1024;

		} else {

			switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) &

drivers/video/riva/riva_hw.c

+8 −4
Original line number Diff line number Diff line
@@ -1118,8 +1118,9 @@ static void nForceUpdateArbitrationSettings 
    unsigned int uMClkPostDiv;

    struct pci_dev *dev;



    dev = pci_find_slot(0, 3);

    dev = pci_get_bus_and_slot(0, 3);

    pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);

    pci_dev_put(dev);

    uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;



    if(!uMClkPostDiv) uMClkPostDiv = 4;
@@ -1132,8 +1133,9 @@ static void nForceUpdateArbitrationSettings 
    sim_data.enable_video   = 0;

    sim_data.enable_mp      = 0;



    dev = pci_find_slot(0, 1);

    dev = pci_get_bus_and_slot(0, 1);

    pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);

    pci_dev_put(dev);

    sim_data.memory_type    = (sim_data.memory_type >> 12) & 1;



    sim_data.memory_width   = 64;
@@ -2112,12 +2114,14 @@ static void nv10GetConfig 
     * Fill in chip configuration.

     */

    if(chipset == NV_CHIP_IGEFORCE2) {

        dev = pci_find_slot(0, 1);

        dev = pci_get_bus_and_slot(0, 1);

        pci_read_config_dword(dev, 0x7C, &amt);

        pci_dev_put(dev);

        chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;

    } else if(chipset == NV_CHIP_0x01F0) {

        dev = pci_find_slot(0, 1);

        dev = pci_get_bus_and_slot(0, 1);

        pci_read_config_dword(dev, 0x84, &amt);

        pci_dev_put(dev);

        chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;

    } else {

        switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF)

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