Commit d3694667 authored by Tom Lendacky's avatar Tom Lendacky Committed by Paolo Bonzini
Browse files

KVM: SVM: Add support for SEV-ES GHCB MSR protocol function 0x004 



The GHCB specification defines a GHCB MSR protocol using the lower
12-bits of the GHCB MSR (in the hypervisor this corresponds to the
GHCB GPA field in the VMCB).

Function 0x004 is a request for CPUID information. Only a single CPUID
result register can be sent per invocation, so the protocol defines the
register that is requested. The GHCB MSR value is set to the CPUID
register value as per the specification via the VMCB GHCB GPA field.

Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Message-Id: <fd7ee347d3936e484c06e9001e340bf6387092cd.1607620209.git.thomas.lendacky@amd.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 1edc1459

arch/x86/kvm/svm/sev.c

+54 −2
Original line number Diff line number Diff line
@@ -1500,6 +1500,18 @@ void pre_sev_run(struct vcpu_svm *svm, int cpu) 
	vmcb_mark_dirty(svm->vmcb, VMCB_ASID);

}



static void set_ghcb_msr_bits(struct vcpu_svm *svm, u64 value, u64 mask,

			      unsigned int pos)

{

	svm->vmcb->control.ghcb_gpa &= ~(mask << pos);

	svm->vmcb->control.ghcb_gpa |= (value & mask) << pos;

}



static u64 get_ghcb_msr_bits(struct vcpu_svm *svm, u64 mask, unsigned int pos)

{

	return (svm->vmcb->control.ghcb_gpa >> pos) & mask;

}



static void set_ghcb_msr(struct vcpu_svm *svm, u64 value)

{

	svm->vmcb->control.ghcb_gpa = value;
@@ -1508,7 +1520,9 @@ static void set_ghcb_msr(struct vcpu_svm *svm, u64 value) 
static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm)

{

	struct vmcb_control_area *control = &svm->vmcb->control;

	struct kvm_vcpu *vcpu = &svm->vcpu;

	u64 ghcb_info;

	int ret = 1;



	ghcb_info = control->ghcb_gpa & GHCB_MSR_INFO_MASK;
@@ -1518,11 +1532,49 @@ static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) 
						    GHCB_VERSION_MIN,

						    sev_enc_bit));

		break;

	case GHCB_MSR_CPUID_REQ: {

		u64 cpuid_fn, cpuid_reg, cpuid_value;



		cpuid_fn = get_ghcb_msr_bits(svm,

					     GHCB_MSR_CPUID_FUNC_MASK,

					     GHCB_MSR_CPUID_FUNC_POS);



		/* Initialize the registers needed by the CPUID intercept */

		vcpu->arch.regs[VCPU_REGS_RAX] = cpuid_fn;

		vcpu->arch.regs[VCPU_REGS_RCX] = 0;



		ret = svm_invoke_exit_handler(svm, SVM_EXIT_CPUID);

		if (!ret) {

			ret = -EINVAL;

			break;

		}



		cpuid_reg = get_ghcb_msr_bits(svm,

					      GHCB_MSR_CPUID_REG_MASK,

					      GHCB_MSR_CPUID_REG_POS);

		if (cpuid_reg == 0)

			cpuid_value = vcpu->arch.regs[VCPU_REGS_RAX];

		else if (cpuid_reg == 1)

			cpuid_value = vcpu->arch.regs[VCPU_REGS_RBX];

		else if (cpuid_reg == 2)

			cpuid_value = vcpu->arch.regs[VCPU_REGS_RCX];

		else

			cpuid_value = vcpu->arch.regs[VCPU_REGS_RDX];



		set_ghcb_msr_bits(svm, cpuid_value,

				  GHCB_MSR_CPUID_VALUE_MASK,

				  GHCB_MSR_CPUID_VALUE_POS);



		set_ghcb_msr_bits(svm, GHCB_MSR_CPUID_RESP,

				  GHCB_MSR_INFO_MASK,

				  GHCB_MSR_INFO_POS);

		break;

	}

	default:

		return -EINVAL;

		ret = -EINVAL;

	}



	return 1;

	return ret;

}



int sev_handle_vmgexit(struct vcpu_svm *svm)

arch/x86/kvm/svm/svm.h

+9 −0
Original line number Diff line number Diff line
@@ -534,6 +534,15 @@ void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); 
	 (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) |	\

	 GHCB_MSR_SEV_INFO_RESP)



#define GHCB_MSR_CPUID_REQ		0x004

#define GHCB_MSR_CPUID_RESP		0x005

#define GHCB_MSR_CPUID_FUNC_POS		32

#define GHCB_MSR_CPUID_FUNC_MASK	0xffffffff

#define GHCB_MSR_CPUID_VALUE_POS	32

#define GHCB_MSR_CPUID_VALUE_MASK	0xffffffff

#define GHCB_MSR_CPUID_REG_POS		30

#define GHCB_MSR_CPUID_REG_MASK		0x3



extern unsigned int max_sev_asid;



static inline bool svm_sev_enabled(void)

CRA Git | Maintained and supported by SUSTech CRA and CCSE