Commit d35c595b authored by Sean V Kelley's avatar Sean V Kelley Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events arm64: Revise core JSON events for eMAG 

Split the PMU events into meaningful functional groups.  Update core pmu
events based on supported ARMv8 recommended IMPLEMENTATION DEFINED
events.

The JSON files are updated with reference to a PMU table shared here:

  https://github.com/AmpereComputing/ampere-centos-kernel/blob/amp-centos-7.5-kernel/Documentation/arm64/eMAG-ARM-CoreImpDefined.pdf



Changes in v3:
- Removed CHAIN event as it wouldn't be useful in Perf - William
- Will factor out events 0x00-0x38 in a follow-on patch - William
- to armv8-recommended.json
Changes in V2:
- Provided documentation for changes - John, William
- Broke up into meaningful groups - William

Signed-off-by: default avatarSean V Kelley <seanvk.dev@oregontracks.org>
Reviewed-by: default avatarWilliam Cohen <wcohen@redhat.com>
Cc: John Garry <john.garry@huawei.com>
Cc: linux-arm-kernel@lists.infradead.org
LPU-Reference: 20180916221203.7935-1-seanvk.dev@oregontracks.org
Link: https://lkml.kernel.org/n/tip-tzvs1ip6srcv2et0ny58e0wy@git.kernel.org


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent bea63857

tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json

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Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "BR_IMMED_SPEC",

    },

    {

        "ArchStdEvent": "BR_RETURN_SPEC",

    },

    {

        "ArchStdEvent": "BR_INDIRECT_SPEC",

    },

    {

        "PublicDescription": "Mispredicted or not predicted branch speculatively executed",

        "EventCode": "0x10",

        "EventName": "BR_MIS_PRED",

        "BriefDescription": "Branch mispredicted"

    },

    {

        "PublicDescription": "Predictable branch speculatively executed",

        "EventCode": "0x12",

        "EventName": "BR_PRED",

        "BriefDescription": "Predictable branch"

    },

]

tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json→tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json

+26 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "L1D_CACHE_RD",

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR",

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_RD",

        "ArchStdEvent": "BUS_ACCESS_RD",

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_WR",

        "ArchStdEvent": "BUS_ACCESS_WR",

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_RD",

        "ArchStdEvent": "BUS_ACCESS_SHARED",

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_WR",

        "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",

    },

    {

        "ArchStdEvent": "L1D_TLB_RD",

        "ArchStdEvent": "BUS_ACCESS_NORMAL",

    },

    {

        "ArchStdEvent": "L1D_TLB_WR",

        "ArchStdEvent": "BUS_ACCESS_PERIPH",

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD",

        "PublicDescription": "Bus access",

        "EventCode": "0x19",

        "EventName": "BUS_ACCESS",

        "BriefDescription": "Bus access"

    },

   {

        "ArchStdEvent": "BUS_ACCESS_WR",

   }

]

tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json

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+191 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "L1D_CACHE_RD",

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR",

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_RD",

    },

    {

        "ArchStdEvent": "L1D_CACHE_INVAL",

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_RD",

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_WR",

    },

    {

        "ArchStdEvent": "L2D_CACHE_RD",

    },

    {

        "ArchStdEvent": "L2D_CACHE_WR",

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_RD",

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_WR",

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_VICTIM",

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_CLEAN",

    },

    {

        "ArchStdEvent": "L2D_CACHE_INVAL",

    },

    {

        "PublicDescription": "Level 1 instruction cache refill",

        "EventCode": "0x01",

        "EventName": "L1I_CACHE_REFILL",

        "BriefDescription": "L1I cache refill"

    },

    {

        "PublicDescription": "Level 1 instruction TLB refill",

        "EventCode": "0x02",

        "EventName": "L1I_TLB_REFILL",

        "BriefDescription": "L1I TLB refill"

    },

    {

        "PublicDescription": "Level 1 data cache refill",

        "EventCode": "0x03",

        "EventName": "L1D_CACHE_REFILL",

        "BriefDescription": "L1D cache refill"

    },

    {

        "PublicDescription": "Level 1 data cache access",

        "EventCode": "0x04",

        "EventName": "L1D_CACHE_ACCESS",

        "BriefDescription": "L1D cache access"

    },

    {

        "PublicDescription": "Level 1 data TLB refill",

        "EventCode": "0x05",

        "EventName": "L1D_TLB_REFILL",

        "BriefDescription": "L1D TLB refill"

    },

    {

        "PublicDescription": "Level 1 instruction cache access",

        "EventCode": "0x14",

        "EventName": "L1I_CACHE_ACCESS",

        "BriefDescription": "L1I cache access"

    },

    {

        "PublicDescription": "Level 2 data cache access",

        "EventCode": "0x16",

        "EventName": "L2D_CACHE_ACCESS",

        "BriefDescription": "L2D cache access"

    },

    {

        "PublicDescription": "Level 2 data refill",

        "EventCode": "0x17",

        "EventName": "L2D_CACHE_REFILL",

        "BriefDescription": "L2D cache refill"

    },

    {

        "PublicDescription": "Level 2 data cache, Write-Back",

        "EventCode": "0x18",

        "EventName": "L2D_CACHE_WB",

        "BriefDescription": "L2D cache Write-Back"

    },

    {

        "PublicDescription": "Level 1 data TLB access. This event counts any load or store operation which accesses the data L1 TLB",

        "EventCode": "0x25",

        "EventName": "L1D_TLB_ACCESS",

        "BriefDescription": "L1D TLB access"

    },

    {

        "PublicDescription": "Level 1 instruction TLB access. This event counts any instruction fetch which accesses the instruction L1 TLB",

        "EventCode": "0x26",

        "EventName": "L1I_TLB_ACCESS",

        "BriefDescription": "L1I TLB access"

    },

    {

        "PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count",

        "EventCode": "0x34",

        "EventName": "L2D_TLB_ACCESS",

        "BriefDescription": "L2D TLB access"

    },

    {

        "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count",

        "EventCode": "0x35",

        "EventName": "L2I_TLB_ACCESS",

        "BriefDescription": "L2D TLB access"

    },

    {

        "PublicDescription": "Branch target buffer misprediction",

        "EventCode": "0x102",

        "EventName": "BTB_MIS_PRED",

        "BriefDescription": "BTB misprediction"

    },

    {

        "PublicDescription": "ITB miss",

        "EventCode": "0x103",

        "EventName": "ITB_MISS",

        "BriefDescription": "ITB miss"

    },

    {

        "PublicDescription": "DTB miss",

        "EventCode": "0x104",

        "EventName": "DTB_MISS",

        "BriefDescription": "DTB miss"

    },

    {

        "PublicDescription": "Level 1 data cache late miss",

        "EventCode": "0x105",

        "EventName": "L1D_CACHE_LATE_MISS",

        "BriefDescription": "L1D cache late miss"

    },

    {

        "PublicDescription": "Level 1 data cache prefetch request",

        "EventCode": "0x106",

        "EventName": "L1D_CACHE_PREFETCH",

        "BriefDescription": "L1D cache prefetch"

    },

    {

        "PublicDescription": "Level 2 data cache prefetch request",

        "EventCode": "0x107",

        "EventName": "L2D_CACHE_PREFETCH",

        "BriefDescription": "L2D cache prefetch"

    },

    {

        "PublicDescription": "Level 1 stage 2 TLB refill",

        "EventCode": "0x111",

        "EventName": "L1_STAGE2_TLB_REFILL",

        "BriefDescription": "L1 stage 2 TLB refill"

    },

    {

        "PublicDescription": "Page walk cache level-0 stage-1 hit",

        "EventCode": "0x112",

        "EventName": "PAGE_WALK_L0_STAGE1_HIT",

        "BriefDescription": "Page walk, L0 stage-1 hit"

    },

    {

        "PublicDescription": "Page walk cache level-1 stage-1 hit",

        "EventCode": "0x113",

        "EventName": "PAGE_WALK_L1_STAGE1_HIT",

        "BriefDescription": "Page walk, L1 stage-1 hit"

    },

    {

        "PublicDescription": "Page walk cache level-2 stage-1 hit",

        "EventCode": "0x114",

        "EventName": "PAGE_WALK_L2_STAGE1_HIT",

        "BriefDescription": "Page walk, L2 stage-1 hit"

    },

    {

        "PublicDescription": "Page walk cache level-1 stage-2 hit",

        "EventCode": "0x115",

        "EventName": "PAGE_WALK_L1_STAGE2_HIT",

        "BriefDescription": "Page walk, L1 stage-2 hit"

    },

    {

        "PublicDescription": "Page walk cache level-2 stage-2 hit",

        "EventCode": "0x116",

        "EventName": "PAGE_WALK_L2_STAGE2_HIT",

        "BriefDescription": "Page walk, L2 stage-2 hit"

    },

]

tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json

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[

    {

        "PublicDescription": "The number of core clock cycles",

        "EventCode": "0x11",

        "EventName": "CPU_CYCLES",

        "BriefDescription": "Clock cycles"

    },

    {

        "PublicDescription": "FSU clocking gated off cycle",

        "EventCode": "0x101",

        "EventName": "FSU_CLOCK_OFF_CYCLES",

        "BriefDescription": "FSU clocking gated off cycle"

    },

    {

        "PublicDescription": "Wait state cycle",

        "EventCode": "0x110",

        "EventName": "Wait_CYCLES",

        "BriefDescription": "Wait state cycle"

    },

]

tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json

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Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "EXC_UNDEF",

    },

    {

        "ArchStdEvent": "EXC_SVC",

    },

    {

        "ArchStdEvent": "EXC_PABORT",

    },

    {

        "ArchStdEvent": "EXC_DABORT",

    },

    {

        "ArchStdEvent": "EXC_IRQ",

    },

    {

        "ArchStdEvent": "EXC_FIQ",

    },

    {

        "ArchStdEvent": "EXC_HVC",

    },

    {

        "ArchStdEvent": "EXC_TRAP_PABORT",

    },

    {

        "ArchStdEvent": "EXC_TRAP_DABORT",

    },

    {

        "ArchStdEvent": "EXC_TRAP_OTHER",

    },

    {

        "ArchStdEvent": "EXC_TRAP_IRQ",

    },

    {

        "ArchStdEvent": "EXC_TRAP_FIQ",

    },

    {

        "PublicDescription": "Exception taken",

        "EventCode": "0x09",

        "EventName": "EXC_TAKEN",

        "BriefDescription": "Exception taken"

    },

    {

        "PublicDescription": "Instruction architecturally executed, condition check pass, exception return",

        "EventCode": "0x0a",

        "EventName": "EXC_RETURN",

        "BriefDescription": "Exception return"

    },

]

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