Commit d31bdabb authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Get num_chans from VBIOS table 



Get the values from VBIOS table

Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1ed0b2dd

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

+98 −0
Original line number Diff line number Diff line
@@ -1378,6 +1378,63 @@ static struct atom_encoder_caps_record *get_encoder_cap_record( 
	return NULL;

}



static enum bp_result get_vram_info_v23(

	struct bios_parser *bp,

	struct dc_vram_info *info)

{

	struct atom_vram_info_header_v2_3 *info_v23;

	enum bp_result result = BP_RESULT_OK;



	info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,

						DATA_TABLES(vram_info));



	if (info_v23 == NULL)

		return BP_RESULT_BADBIOSTABLE;



	info->num_chans = info_v23->vram_module[0].channel_num;

	info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;



	return result;

}



static enum bp_result get_vram_info_v24(

	struct bios_parser *bp,

	struct dc_vram_info *info)

{

	struct atom_vram_info_header_v2_4 *info_v24;

	enum bp_result result = BP_RESULT_OK;



	info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,

						DATA_TABLES(vram_info));



	if (info_v24 == NULL)

		return BP_RESULT_BADBIOSTABLE;



	info->num_chans = info_v24->vram_module[0].channel_num;

	info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8;



	return result;

}



static enum bp_result get_vram_info_v25(

	struct bios_parser *bp,

	struct dc_vram_info *info)

{

	struct atom_vram_info_header_v2_5 *info_v25;

	enum bp_result result = BP_RESULT_OK;



	info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,

						DATA_TABLES(vram_info));



	if (info_v25 == NULL)

		return BP_RESULT_BADBIOSTABLE;



	info->num_chans = info_v25->vram_module[0].channel_num;

	info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8;



	return result;

}



/*

 * get_integrated_info_v11

 *
@@ -1669,6 +1726,46 @@ static enum bp_result construct_integrated_info( 
	return result;

}



static enum bp_result bios_parser_get_vram_info(

		struct dc_bios *dcb,

		struct dc_vram_info *info)

{

	struct bios_parser *bp = BP_FROM_DCB(dcb);

	enum bp_result result = BP_RESULT_BADBIOSTABLE;

	struct atom_common_table_header *header;

	struct atom_data_revision revision;



	if (info && DATA_TABLES(vram_info)) {

		header = GET_IMAGE(struct atom_common_table_header,

					DATA_TABLES(vram_info));



		get_atom_data_table_revision(header, &revision);



		switch (revision.major) {

		case 2:

			switch (revision.minor) {

			case 3:

				result = get_vram_info_v23(bp, info);

				break;

			case 4:

				result = get_vram_info_v24(bp, info);

				break;

			case 5:

				result = get_vram_info_v25(bp, info);

				break;

			default:

				break;

			}

			break;



		default:

			return result;

		}



	}

	return result;

}



static struct integrated_info *bios_parser_create_integrated_info(

	struct dc_bios *dcb)

{
@@ -2112,6 +2209,7 @@ static bool bios_parser2_construct( 


	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);

	bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;

	bios_parser_get_vram_info(&bp->base, &bp->base.vram_info);



	return true;

}

drivers/gpu/drm/amd/display/dc/dc_bios_types.h

+1 −0
Original line number Diff line number Diff line
@@ -153,6 +153,7 @@ struct dc_bios { 
	struct integrated_info *integrated_info;

	struct dc_firmware_info fw_info;

	bool fw_info_valid;

	struct dc_vram_info vram_info;

};



#endif /* DC_BIOS_TYPES_H */

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

+6 −1
Original line number Diff line number Diff line
@@ -195,7 +195,6 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { 
	.max_avg_dram_bw_use_normal_percent = 40.0,

	.writeback_latency_us = 12.0,

	.max_request_size_bytes = 256,

	.dram_channel_width_bytes = 2,

	.fabric_datapath_to_dcn_data_return_bytes = 64,

	.dcn_downspread_percent = 0.5,

	.downspread_percent = 0.38,
@@ -2242,6 +2241,12 @@ static void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw 
{

	unsigned int i;



	if (dc->ctx->dc_bios->vram_info.num_chans)

		dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;



	if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

		dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;



	dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

+5 −0
Original line number Diff line number Diff line
@@ -183,6 +183,11 @@ struct dc_firmware_info { 


};



struct dc_vram_info {

	unsigned int num_chans;

	unsigned int dram_channel_width_bytes;

};



struct step_and_delay_info {

	uint32_t step;

	uint32_t delay;

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