Merge tag 'clk-for-linus-3.14-part2' of git://git.linaro.org/people/mike.turquette/linux

Binding for Texas Instruments APLL clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1].  It assumes a

register-mapped APLL with usually two selectable input clocks

(reference clock and bypass clock), with analog phase locked

loop logic for multiplying the input clock to a desired output

clock. This clock also typically supports different operation

modes (locked, low power stop etc.) APLL mostly behaves like

a subtype of a DPLL [2], although a simplified one at that.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/clock/ti/dpll.txt

Required properties:

- compatible : shall be "ti,dra7-apll-clock"

- #clock-cells : from common clock binding; shall be set to 0.

- clocks : link phandles of parent clocks (clk-ref and clk-bypass)

- reg : address and length of the register set for controlling the APLL.

  It contains the information of registers in the following order:

	"control" - contains the control register base address

	"idlest" - contains the idlest register base address

Examples:

	apll_pcie_ck: apll_pcie_ck@4a008200 {

		#clock-cells = <0>;

		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;

		reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;

		compatible = "ti,dra7-apll-clock";

	};

Binding for Texas Instruments autoidle clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1]. It assumes a register mapped

clock which can be put to idle automatically by hardware based on the usage

and a configuration bit setting. Autoidle clock is never an individual

clock, it is always a derivative of some basic clock like a gate, divider,

or fixed-factor.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:

- reg : offset for the register controlling the autoidle

- ti,autoidle-shift : bit shift of the autoidle enable bit

- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0

Examples:

	dpll_core_m4_ck: dpll_core_m4_ck {

		#clock-cells = <0>;

		compatible = "ti,divider-clock";

		clocks = <&dpll_core_x2_ck>;

		ti,max-div = <31>;

		ti,autoidle-shift = <8>;

		reg = <0x2d38>;

		ti,index-starts-at-one;

		ti,invert-autoidle-bit;

	};

	dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {

		#clock-cells = <0>;

		compatible = "ti,fixed-factor-clock";

		clocks = <&dpll_usb_ck>;

		ti,clock-div = <1>;

		ti,autoidle-shift = <8>;

		reg = <0x01b4>;

		ti,clock-mult = <1>;

		ti,invert-autoidle-bit;

	};

Binding for Texas Instruments clockdomain.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1] in consumer role.

Every clock on TI SoC belongs to one clockdomain, but software

only needs this information for specific clocks which require

their parent clockdomain to be controlled when the clock is

enabled/disabled. This binding doesn't define a new clock

binding type, it is used to group existing clock nodes under

hardware hierarchy.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:

- compatible : shall be "ti,clockdomain"

- #clock-cells : from common clock binding; shall be set to 0.

- clocks : link phandles of clocks within this domain

Examples:

	dss_clkdm: dss_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;

	};

Binding for TI composite clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1]. It assumes a

register-mapped composite clock with multiple different sub-types;

a multiplexer clock with multiple input clock signals or parents, one

of which can be selected as output, this behaves exactly as [2]

an adjustable clock rate divider, this behaves exactly as [3]

a gating function which can be used to enable and disable the output

clock, this behaves exactly as [4]

The binding must provide a list of the component clocks that shall be

merged to this clock. The component clocks shall be of one of the

"ti,*composite*-clock" types.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/clock/ti/mux.txt

[3] Documentation/devicetree/bindings/clock/ti/divider.txt

[4] Documentation/devicetree/bindings/clock/ti/gate.txt

Required properties:

- compatible : shall be: "ti,composite-clock"

- clocks : link phandles of component clocks

- #clock-cells : from common clock binding; shall be set to 0.

Examples:

usb_l4_gate_ick: usb_l4_gate_ick {

	#clock-cells = <0>;

	compatible = "ti,composite-interface-clock";

	clocks = <&l4_ick>;

	ti,bit-shift = <5>;

	reg = <0x0a10>;

};

usb_l4_div_ick: usb_l4_div_ick {

	#clock-cells = <0>;

	compatible = "ti,composite-divider-clock";

	clocks = <&l4_ick>;

	ti,bit-shift = <4>;

	ti,max-div = <1>;

	reg = <0x0a40>;

	ti,index-starts-at-one;

};

usb_l4_ick: usb_l4_ick {

	#clock-cells = <0>;

	compatible = "ti,composite-clock";

	clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;

};

Binding for TI divider clock

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1].  It assumes a

register-mapped adjustable clock rate divider that does not gate and has

only one input clock or parent.  By default the value programmed into

the register is one less than the actual divisor value.  E.g:

register value		actual divisor value

0			1

1			2

2			3

This assumption may be modified by the following optional properties:

ti,index-starts-at-one - valid divisor values start at 1, not the default

of 0.  E.g:

register value		actual divisor value

1			1

2			2

3			3

ti,index-power-of-two - valid divisor values are powers of two.  E.g:

register value		actual divisor value

0			1

1			2

2			4

Additionally an array of valid dividers may be supplied like so:

	ti,dividers = <4>, <8>, <0>, <16>;

Which will map the resulting values to a divisor table by their index:

register value		actual divisor value

0			4

1			8

2			<invalid divisor, skipped>

3			16

Any zero value in this array means the corresponding bit-value is invalid

and must not be used.

The binding must also provide the register to control the divider and

unless the divider array is provided, min and max dividers. Optionally

the number of bits to shift that mask, if necessary. If the shift value

is missing it is the same as supplying a zero shift.

This binding can also optionally provide support to the hardware autoidle

feature, see [2].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt

Required properties:

- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".

- #clock-cells : from common clock binding; shall be set to 0.

- clocks : link to phandle of parent clock

- reg : offset for register controlling adjustable divider

Optional properties:

- clock-output-names : from common clock binding.

- ti,dividers : array of integers defining divisors

- ti,bit-shift : number of bits to shift the divider value, defaults to 0

- ti,min-div : min divisor for dividing the input clock rate, only

  needed if the first divisor is offset from the default value (1)

- ti,max-div : max divisor for dividing the input clock rate, only needed

  if ti,dividers is not defined.

- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,

  only valid if ti,dividers is not defined.

- ti,index-power-of-two : valid divisor programming must be a power of two,

  only valid if ti,dividers is not defined.

- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,

  see [2]

- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,

  see [2]

- ti,set-rate-parent : clk_set_rate is propagated to parent

Examples:

dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {

	#clock-cells = <0>;

	compatible = "ti,divider-clock";

	clocks = <&dpll_usb_ck>;

	ti,max-div = <127>;

	reg = <0x190>;

	ti,index-starts-at-one;

};

aess_fclk: aess_fclk@4a004528 {

	#clock-cells = <0>;

	compatible = "ti,divider-clock";

	clocks = <&abe_clk>;

	ti,bit-shift = <24>;

	reg = <0x528>;

	ti,max-div = <2>;

};

dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {

	#clock-cells = <0>;

	compatible = "ti,composite-divider-clock";

	clocks = <&dpll_core_x2_ck>;

	ti,max-div = <31>;

	reg = <0x0134>;

	ti,index-starts-at-one;

};

ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {

	#clock-cells = <0>;

	compatible = "ti,composite-divider-clock";

	clocks = <&corex2_fck>;

	ti,bit-shift = <8>;

	reg = <0x0a40>;

	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;

};