Commit d2c0bdaa authored by Jarkko Nikula's avatar Jarkko Nikula Committed by Mark Brown
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ASoC: OMAP: Add functionality to set CLKR and FSR sources in McBSP DAI 



The McBSP1 port in OMAP3 processors (I believe OMAP2 too but I don't have
specifications to check it) have additional CLKR and FSR pins for McBSP1
receiver. Reset default is that receiver is using bit clock and frame
sync signal from those pins but it is possible to configure to use
also CLKX and FSX pins as well. In fact, other McBSP ports are doing that
internally that transmitter and receiver share the CLKX and FSX.

Add functionaly that machine drivers can set the CLKR and FSR sources by
using the snd_soc_dai_set_sysclk.

Thanks to "Aggarwal, Anuj" <anuj.aggarwal@ti.com> for reporting the issue.

Signed-off-by: default avatarJarkko Nikula <jhnikula@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent f4890b5c

sound/soc/omap/omap-mcbsp.c

+41 −0
Original line number Diff line number Diff line
@@ -512,6 +512,40 @@ static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data, 
	return 0;

}



static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,

				       int clk_id)

{

	int sel_bit, set = 0;

	u16 reg = OMAP2_CONTROL_DEVCONF0;



	if (cpu_class_is_omap1())

		return -EINVAL; /* TODO: Can this be implemented for OMAP1? */

	if (mcbsp_data->bus_id != 0)

		return -EINVAL;



	switch (clk_id) {

	case OMAP_MCBSP_CLKR_SRC_CLKX:

		set = 1;

	case OMAP_MCBSP_CLKR_SRC_CLKR:

		sel_bit = 3;

		break;

	case OMAP_MCBSP_FSR_SRC_FSX:

		set = 1;

	case OMAP_MCBSP_FSR_SRC_FSR:

		sel_bit = 4;

		break;

	default:

		return -EINVAL;

	}



	if (set)

		omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);

	else

		omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);



	return 0;

}



static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,

					 int clk_id, unsigned int freq,

					 int dir)
@@ -534,6 +568,13 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 
	case OMAP_MCBSP_SYSCLK_CLKR_EXT:

		regs->pcr0	|= SCLKME;

		break;



	case OMAP_MCBSP_CLKR_SRC_CLKR:

	case OMAP_MCBSP_CLKR_SRC_CLKX:

	case OMAP_MCBSP_FSR_SRC_FSR:

	case OMAP_MCBSP_FSR_SRC_FSX:

		err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);

		break;

	default:

		err = -ENODEV;

	}

sound/soc/omap/omap-mcbsp.h

+4 −0
Original line number Diff line number Diff line
@@ -32,6 +32,10 @@ enum omap_mcbsp_clksrg_clk { 
	OMAP_MCBSP_SYSCLK_CLK,		/* Internal ICLK */

	OMAP_MCBSP_SYSCLK_CLKX_EXT,	/* External CLKX pin */

	OMAP_MCBSP_SYSCLK_CLKR_EXT,	/* External CLKR pin */

	OMAP_MCBSP_CLKR_SRC_CLKR,	/* CLKR from CLKR pin */

	OMAP_MCBSP_CLKR_SRC_CLKX,	/* CLKR from CLKX pin */

	OMAP_MCBSP_FSR_SRC_FSR,		/* FSR from FSR pin */

	OMAP_MCBSP_FSR_SRC_FSX,		/* FSR from FSX pin */

};



/* McBSP dividers */

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