Commit d2bea739 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 apic changes from Ingo Molnar:
 "The main changes in this cycle were:

   - Numachip updates: new hardware support, fixes and cleanups.
     (Daniel J Blueman)

   - misc smaller cleanups and fixlets"

* 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/io_apic: Make eoi_ioapic_pin() static
  x86/irq: Drop unlikely before IS_ERR_OR_NULL
  x86/x2apic: Make stub functions available even if !CONFIG_X86_LOCAL_APIC
  x86/apic: Deinline various functions
  x86/numachip: Fix timer build conflict
  x86/numachip: Introduce Numachip2 timer mechanisms
  x86/numachip: Add Numachip IPI optimisations
  x86/numachip: Add Numachip2 APIC support
  x86/numachip: Cleanup Numachip support
parents 53528695 4faefda9

arch/x86/include/asm/apic.h

+55 −55
Original line number Diff line number Diff line
@@ -115,6 +115,59 @@ static inline bool apic_is_x2apic_enabled(void) 
	return msr & X2APIC_ENABLE;

}



extern void enable_IR_x2apic(void);



extern int get_physical_broadcast(void);



extern int lapic_get_maxlvt(void);

extern void clear_local_APIC(void);

extern void disconnect_bsp_APIC(int virt_wire_setup);

extern void disable_local_APIC(void);

extern void lapic_shutdown(void);

extern void sync_Arb_IDs(void);

extern void init_bsp_APIC(void);

extern void setup_local_APIC(void);

extern void init_apic_mappings(void);

void register_lapic_address(unsigned long address);

extern void setup_boot_APIC_clock(void);

extern void setup_secondary_APIC_clock(void);

extern int APIC_init_uniprocessor(void);



#ifdef CONFIG_X86_64

static inline int apic_force_enable(unsigned long addr)

{

	return -1;

}

#else

extern int apic_force_enable(unsigned long addr);

#endif



extern int apic_bsp_setup(bool upmode);

extern void apic_ap_setup(void);



/*

 * On 32bit this is mach-xxx local

 */

#ifdef CONFIG_X86_64

extern int apic_is_clustered_box(void);

#else

static inline int apic_is_clustered_box(void)

{

	return 0;

}

#endif



extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);



#else /* !CONFIG_X86_LOCAL_APIC */

static inline void lapic_shutdown(void) { }

#define local_apic_timer_c2_ok		1

static inline void init_apic_mappings(void) { }

static inline void disable_local_APIC(void) { }

# define setup_boot_APIC_clock x86_init_noop

# define setup_secondary_APIC_clock x86_init_noop

#endif /* !CONFIG_X86_LOCAL_APIC */



#ifdef CONFIG_X86_X2APIC

/*

 * Make previous memory operations globally visible before
@@ -186,67 +239,14 @@ static inline int x2apic_enabled(void) 
}



#define x2apic_supported()	(cpu_has_x2apic)

#else

#else /* !CONFIG_X86_X2APIC */

static inline void check_x2apic(void) { }

static inline void x2apic_setup(void) { }

static inline int x2apic_enabled(void) { return 0; }



#define x2apic_mode		(0)

#define	x2apic_supported()	(0)

#endif



extern void enable_IR_x2apic(void);



extern int get_physical_broadcast(void);



extern int lapic_get_maxlvt(void);

extern void clear_local_APIC(void);

extern void disconnect_bsp_APIC(int virt_wire_setup);

extern void disable_local_APIC(void);

extern void lapic_shutdown(void);

extern void sync_Arb_IDs(void);

extern void init_bsp_APIC(void);

extern void setup_local_APIC(void);

extern void init_apic_mappings(void);

void register_lapic_address(unsigned long address);

extern void setup_boot_APIC_clock(void);

extern void setup_secondary_APIC_clock(void);

extern int APIC_init_uniprocessor(void);



#ifdef CONFIG_X86_64

static inline int apic_force_enable(unsigned long addr)

{

	return -1;

}

#else

extern int apic_force_enable(unsigned long addr);

#endif



extern int apic_bsp_setup(bool upmode);

extern void apic_ap_setup(void);



/*

 * On 32bit this is mach-xxx local

 */

#ifdef CONFIG_X86_64

extern int apic_is_clustered_box(void);

#else

static inline int apic_is_clustered_box(void)

{

	return 0;

}

#endif



extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);



#else /* !CONFIG_X86_LOCAL_APIC */

static inline void lapic_shutdown(void) { }

#define local_apic_timer_c2_ok		1

static inline void init_apic_mappings(void) { }

static inline void disable_local_APIC(void) { }

# define setup_boot_APIC_clock x86_init_noop

# define setup_secondary_APIC_clock x86_init_noop

#endif /* !CONFIG_X86_LOCAL_APIC */

#endif /* !CONFIG_X86_X2APIC */



#ifdef CONFIG_X86_64

#define	SET_APIC_ID(x)		(apic->set_apic_id(x))

arch/x86/include/asm/numachip/numachip.h

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#ifndef _ASM_X86_NUMACHIP_NUMACHIP_H

#define _ASM_X86_NUMACHIP_NUMACHIP_H



extern u8 numachip_system;

extern int __init pci_numachip_init(void);



#endif /* _ASM_X86_NUMACHIP_NUMACHIP_H */

arch/x86/include/asm/numachip/numachip_csr.h

+42 −111
Original line number Diff line number Diff line
@@ -14,12 +14,8 @@ 
#ifndef _ASM_X86_NUMACHIP_NUMACHIP_CSR_H

#define _ASM_X86_NUMACHIP_NUMACHIP_CSR_H



#include <linux/numa.h>

#include <linux/percpu.h>

#include <linux/smp.h>

#include <linux/io.h>

#include <linux/swab.h>

#include <asm/types.h>

#include <asm/processor.h>



#define CSR_NODE_SHIFT		16

#define CSR_NODE_BITS(p)	(((unsigned long)(p)) << CSR_NODE_SHIFT)
@@ -27,11 +23,8 @@ 


/* 32K CSR space, b15 indicates geo/non-geo */

#define CSR_OFFSET_MASK	0x7fffUL



/* Global CSR space covers all 4K possible nodes with 64K CSR space per node */

#define NUMACHIP_GCSR_BASE	0x3fff00000000ULL

#define NUMACHIP_GCSR_LIM	0x3fff0fffffffULL

#define NUMACHIP_GCSR_SIZE	(NUMACHIP_GCSR_LIM - NUMACHIP_GCSR_BASE + 1)

#define CSR_G0_NODE_IDS (0x008 + (0 << 12))

#define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))



/*

 * Local CSR space starts in global CSR space with "nodeid" = 0xfff0, however
@@ -41,12 +34,7 @@ 
#define NUMACHIP_LCSR_BASE	0x3ffffe000000ULL

#define NUMACHIP_LCSR_LIM	0x3fffffffffffULL

#define NUMACHIP_LCSR_SIZE	(NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)



static inline void *gcsr_address(int node, unsigned long offset)

{

	return __va(NUMACHIP_GCSR_BASE | (1UL << 15) |

		CSR_NODE_BITS(node & CSR_NODE_MASK) | (offset & CSR_OFFSET_MASK));

}

#define NUMACHIP_LAPIC_BITS	8



static inline void *lcsr_address(unsigned long offset)

{
@@ -54,114 +42,57 @@ static inline void *lcsr_address(unsigned long offset) 
		CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK));

}



static inline unsigned int read_gcsr(int node, unsigned long offset)

static inline unsigned int read_lcsr(unsigned long offset)

{

	return swab32(readl(gcsr_address(node, offset)));

	return swab32(readl(lcsr_address(offset)));

}



static inline void write_gcsr(int node, unsigned long offset, unsigned int val)

static inline void write_lcsr(unsigned long offset, unsigned int val)

{

	writel(swab32(val), gcsr_address(node, offset));

	writel(swab32(val), lcsr_address(offset));

}



static inline unsigned int read_lcsr(unsigned long offset)

/*

 * On NumaChip2, local CSR space is 16MB and starts at fixed offset below 4G

 */



#define NUMACHIP2_LCSR_BASE       0xf0000000UL

#define NUMACHIP2_LCSR_SIZE       0x1000000UL

#define NUMACHIP2_APIC_ICR        0x100000

#define NUMACHIP2_TIMER_DEADLINE  0x200000

#define NUMACHIP2_TIMER_INT       0x200008

#define NUMACHIP2_TIMER_NOW       0x200018

#define NUMACHIP2_TIMER_RESET     0x200020



static inline void __iomem *numachip2_lcsr_address(unsigned long offset)

{

	return swab32(readl(lcsr_address(offset)));

	return (void __iomem *)__va(NUMACHIP2_LCSR_BASE |

		(offset & (NUMACHIP2_LCSR_SIZE - 1)));

}



static inline void write_lcsr(unsigned long offset, unsigned int val)

static inline u32 numachip2_read32_lcsr(unsigned long offset)

{

	writel(swab32(val), lcsr_address(offset));

	return readl(numachip2_lcsr_address(offset));

}



/* ========================================================================= */

/*                   CSR_G0_STATE_CLEAR                                      */

/* ========================================================================= */



#define CSR_G0_STATE_CLEAR (0x000 + (0 << 12))

union numachip_csr_g0_state_clear {

	unsigned int v;

	struct numachip_csr_g0_state_clear_s {

		unsigned int _state:2;

		unsigned int _rsvd_2_6:5;

		unsigned int _lost:1;

		unsigned int _rsvd_8_31:24;

	} s;

};



/* ========================================================================= */

/*                   CSR_G0_NODE_IDS                                         */

/* ========================================================================= */

static inline u64 numachip2_read64_lcsr(unsigned long offset)

{

	return readq(numachip2_lcsr_address(offset));

}



#define CSR_G0_NODE_IDS (0x008 + (0 << 12))

union numachip_csr_g0_node_ids {

	unsigned int v;

	struct numachip_csr_g0_node_ids_s {

		unsigned int _initialid:16;

		unsigned int _nodeid:12;

		unsigned int _rsvd_28_31:4;

	} s;

};



/* ========================================================================= */

/*                   CSR_G3_EXT_IRQ_GEN                                      */

/* ========================================================================= */

static inline void numachip2_write32_lcsr(unsigned long offset, u32 val)

{

	writel(val, numachip2_lcsr_address(offset));

}



#define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))

union numachip_csr_g3_ext_irq_gen {

	unsigned int v;

	struct numachip_csr_g3_ext_irq_gen_s {

		unsigned int _vector:8;

		unsigned int _msgtype:3;

		unsigned int _index:5;

		unsigned int _destination_apic_id:16;

	} s;

};



/* ========================================================================= */

/*                   CSR_G3_EXT_IRQ_STATUS                                   */

/* ========================================================================= */



#define CSR_G3_EXT_IRQ_STATUS (0x034 + (3 << 12))

union numachip_csr_g3_ext_irq_status {

	unsigned int v;

	struct numachip_csr_g3_ext_irq_status_s {

		unsigned int _result:32;

	} s;

};



/* ========================================================================= */

/*                   CSR_G3_EXT_IRQ_DEST                                     */

/* ========================================================================= */



#define CSR_G3_EXT_IRQ_DEST (0x038 + (3 << 12))

union numachip_csr_g3_ext_irq_dest {

	unsigned int v;

	struct numachip_csr_g3_ext_irq_dest_s {

		unsigned int _irq:8;

		unsigned int _rsvd_8_31:24;

	} s;

};



/* ========================================================================= */

/*                   CSR_G3_NC_ATT_MAP_SELECT                                */

/* ========================================================================= */



#define CSR_G3_NC_ATT_MAP_SELECT (0x7fc + (3 << 12))

union numachip_csr_g3_nc_att_map_select {

	unsigned int v;

	struct numachip_csr_g3_nc_att_map_select_s {

		unsigned int _upper_address_bits:4;

		unsigned int _select_ram:4;

		unsigned int _rsvd_8_31:24;

	} s;

};



/* ========================================================================= */

/*                   CSR_G3_NC_ATT_MAP_SELECT_0-255                          */

/* ========================================================================= */



#define CSR_G3_NC_ATT_MAP_SELECT_0 (0x800 + (3 << 12))

static inline void numachip2_write64_lcsr(unsigned long offset, u64 val)

{

	writeq(val, numachip2_lcsr_address(offset));

}



#endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */

static inline unsigned int numachip2_timer(void)

{

	return (smp_processor_id() % 48) << 6;

}



#endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */

arch/x86/kernel/apic/apic.c

+4 −4
Original line number Diff line number Diff line
@@ -1431,7 +1431,7 @@ enum { 
};

static int x2apic_state;



static inline void __x2apic_disable(void)

static void __x2apic_disable(void)

{

	u64 msr;
@@ -1447,7 +1447,7 @@ static inline void __x2apic_disable(void) 
	printk_once(KERN_INFO "x2apic disabled\n");

}



static inline void __x2apic_enable(void)

static void __x2apic_enable(void)

{

	u64 msr;
@@ -1807,7 +1807,7 @@ int apic_version[MAX_LOCAL_APIC]; 
/*

 * This interrupt should _never_ happen with our APIC/SMP architecture

 */

static inline void __smp_spurious_interrupt(u8 vector)

static void __smp_spurious_interrupt(u8 vector)

{

	u32 v;
@@ -1848,7 +1848,7 @@ __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) 
/*

 * This interrupt should never happen with our APIC/SMP architecture

 */

static inline void __smp_error_interrupt(struct pt_regs *regs)

static void __smp_error_interrupt(struct pt_regs *regs)

{

	u32 v;

	u32 i = 0;

arch/x86/kernel/apic/apic_numachip.c

+160 −60
Original line number Diff line number Diff line
@@ -11,30 +11,21 @@ 
 *

 */



#include <linux/errno.h>

#include <linux/threads.h>

#include <linux/cpumask.h>

#include <linux/string.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/ctype.h>

#include <linux/init.h>

#include <linux/hardirq.h>

#include <linux/delay.h>



#include <asm/numachip/numachip.h>

#include <asm/numachip/numachip_csr.h>

#include <asm/smp.h>

#include <asm/apic.h>

#include <asm/ipi.h>

#include <asm/apic_flat_64.h>

#include <asm/pgtable.h>

#include <asm/pci_x86.h>



static int numachip_system __read_mostly;

u8 numachip_system __read_mostly;

static const struct apic apic_numachip1;

static const struct apic apic_numachip2;

static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly;



static const struct apic apic_numachip;



static unsigned int get_apic_id(unsigned long x)

static unsigned int numachip1_get_apic_id(unsigned long x)

{

	unsigned long value;

	unsigned int id = (x >> 24) & 0xff;
@@ -47,7 +38,7 @@ static unsigned int get_apic_id(unsigned long x) 
	return id;

}



static unsigned long set_apic_id(unsigned int id)

static unsigned long numachip1_set_apic_id(unsigned int id)

{

	unsigned long x;
@@ -55,9 +46,17 @@ static unsigned long set_apic_id(unsigned int id) 
	return x;

}



static unsigned int read_xapic_id(void)

static unsigned int numachip2_get_apic_id(unsigned long x)

{

	u64 mcfg;



	rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg);

	return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24);

}



static unsigned long numachip2_set_apic_id(unsigned int id)

{

	return get_apic_id(apic_read(APIC_ID));

	return id << 24;

}



static int numachip_apic_id_valid(int apicid)
@@ -68,7 +67,7 @@ static int numachip_apic_id_valid(int apicid) 


static int numachip_apic_id_registered(void)

{

	return physid_isset(read_xapic_id(), phys_cpu_present_map);

	return 1;

}



static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
@@ -76,36 +75,48 @@ static int numachip_phys_pkg_id(int initial_apic_id, int index_msb) 
	return initial_apic_id >> index_msb;

}



static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)

static void numachip1_apic_icr_write(int apicid, unsigned int val)

{

	union numachip_csr_g3_ext_irq_gen int_gen;



	int_gen.s._destination_apic_id = phys_apicid;

	int_gen.s._vector = 0;

	int_gen.s._msgtype = APIC_DM_INIT >> 8;

	int_gen.s._index = 0;



	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);

	write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val);

}



	int_gen.s._msgtype = APIC_DM_STARTUP >> 8;

	int_gen.s._vector = start_rip >> 12;

static void numachip2_apic_icr_write(int apicid, unsigned int val)

{

	numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val);

}



	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);

static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)

{

	numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);

	numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |

		(start_rip >> 12));



	return 0;

}



static void numachip_send_IPI_one(int cpu, int vector)

{

	union numachip_csr_g3_ext_irq_gen int_gen;

	int apicid = per_cpu(x86_cpu_to_apicid, cpu);



	int_gen.s._destination_apic_id = apicid;

	int_gen.s._vector = vector;

	int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8;

	int_gen.s._index = 0;

	int local_apicid, apicid = per_cpu(x86_cpu_to_apicid, cpu);

	unsigned int dmode;



	preempt_disable();

	local_apicid = __this_cpu_read(x86_cpu_to_apicid);



	/* Send via local APIC where non-local part matches */

	if (!((apicid ^ local_apicid) >> NUMACHIP_LAPIC_BITS)) {

		unsigned long flags;



		local_irq_save(flags);

		__default_send_IPI_dest_field(apicid, vector,

			APIC_DEST_PHYSICAL);

		local_irq_restore(flags);

		preempt_enable();

		return;

	}

	preempt_enable();



	write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);

	dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED;

	numachip_apic_icr_write(apicid, dmode | vector);

}



static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
@@ -149,9 +160,14 @@ static void numachip_send_IPI_self(int vector) 
	apic_write(APIC_SELF_IPI, vector);

}



static int __init numachip_probe(void)

static int __init numachip1_probe(void)

{

	return apic == &apic_numachip;

	return apic == &apic_numachip1;

}



static int __init numachip2_probe(void)

{

	return apic == &apic_numachip2;

}



static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
@@ -172,34 +188,118 @@ static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) 


static int __init numachip_system_init(void)

{

	if (!numachip_system)

		return 0;



	/* Map the LCSR area and set up the apic_icr_write function */

	switch (numachip_system) {

	case 1:

		init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);

	init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);

		numachip_apic_icr_write = numachip1_apic_icr_write;

		x86_init.pci.arch_init = pci_numachip_init;

		break;

	case 2:

		init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE);

		numachip_apic_icr_write = numachip2_apic_icr_write;



		/* Use MCFG config cycles rather than locked CF8 cycles */

		raw_pci_ops = &pci_mmcfg;

		break;

	default:

		return 0;

	}



	x86_cpuinit.fixup_cpu_id = fixup_cpu_id;

	x86_init.pci.arch_init = pci_numachip_init;



	return 0;

}

early_initcall(numachip_system_init);



static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)

static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id)

{

	if (!strncmp(oem_id, "NUMASC", 6)) {

	if ((strncmp(oem_id, "NUMASC", 6) != 0) ||

	    (strncmp(oem_table_id, "NCONNECT", 8) != 0))

		return 0;



	numachip_system = 1;



	return 1;

}



static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id)

{

	if ((strncmp(oem_id, "NUMASC", 6) != 0) ||

	    (strncmp(oem_table_id, "NCONECT2", 8) != 0))

		return 0;



	numachip_system = 2;



	return 1;

}



/* APIC IPIs are queued */

static void numachip_apic_wait_icr_idle(void)

{

}



static const struct apic apic_numachip __refconst = {

/* APIC NMI IPIs are queued */

static u32 numachip_safe_apic_wait_icr_idle(void)

{

	return 0;

}



static const struct apic apic_numachip1 __refconst = {

	.name				= "NumaConnect system",

	.probe				= numachip_probe,

	.acpi_madt_oem_check		= numachip_acpi_madt_oem_check,

	.probe				= numachip1_probe,

	.acpi_madt_oem_check		= numachip1_acpi_madt_oem_check,

	.apic_id_valid			= numachip_apic_id_valid,

	.apic_id_registered		= numachip_apic_id_registered,



	.irq_delivery_mode		= dest_Fixed,

	.irq_dest_mode			= 0, /* physical */



	.target_cpus			= online_target_cpus,

	.disable_esr			= 0,

	.dest_logical			= 0,

	.check_apicid_used		= NULL,



	.vector_allocation_domain	= default_vector_allocation_domain,

	.init_apic_ldr			= flat_init_apic_ldr,



	.ioapic_phys_id_map		= NULL,

	.setup_apic_routing		= NULL,

	.cpu_present_to_apicid		= default_cpu_present_to_apicid,

	.apicid_to_cpu_present		= NULL,

	.check_phys_apicid_present	= default_check_phys_apicid_present,

	.phys_pkg_id			= numachip_phys_pkg_id,



	.get_apic_id			= numachip1_get_apic_id,

	.set_apic_id			= numachip1_set_apic_id,

	.apic_id_mask			= 0xffU << 24,



	.cpu_mask_to_apicid_and		= default_cpu_mask_to_apicid_and,



	.send_IPI_mask			= numachip_send_IPI_mask,

	.send_IPI_mask_allbutself	= numachip_send_IPI_mask_allbutself,

	.send_IPI_allbutself		= numachip_send_IPI_allbutself,

	.send_IPI_all			= numachip_send_IPI_all,

	.send_IPI_self			= numachip_send_IPI_self,



	.wakeup_secondary_cpu		= numachip_wakeup_secondary,

	.inquire_remote_apic		= NULL, /* REMRD not supported */



	.read				= native_apic_mem_read,

	.write				= native_apic_mem_write,

	.eoi_write			= native_apic_mem_write,

	.icr_read			= native_apic_icr_read,

	.icr_write			= native_apic_icr_write,

	.wait_icr_idle			= numachip_apic_wait_icr_idle,

	.safe_wait_icr_idle		= numachip_safe_apic_wait_icr_idle,

};



apic_driver(apic_numachip1);



static const struct apic apic_numachip2 __refconst = {

	.name				= "NumaConnect2 system",

	.probe				= numachip2_probe,

	.acpi_madt_oem_check		= numachip2_acpi_madt_oem_check,

	.apic_id_valid			= numachip_apic_id_valid,

	.apic_id_registered		= numachip_apic_id_registered,
@@ -221,8 +321,8 @@ static const struct apic apic_numachip __refconst = { 
	.check_phys_apicid_present	= default_check_phys_apicid_present,

	.phys_pkg_id			= numachip_phys_pkg_id,



	.get_apic_id			= get_apic_id,

	.set_apic_id			= set_apic_id,

	.get_apic_id			= numachip2_get_apic_id,

	.set_apic_id			= numachip2_set_apic_id,

	.apic_id_mask			= 0xffU << 24,



	.cpu_mask_to_apicid_and		= default_cpu_mask_to_apicid_and,
@@ -241,8 +341,8 @@ static const struct apic apic_numachip __refconst = { 
	.eoi_write			= native_apic_mem_write,

	.icr_read			= native_apic_icr_read,

	.icr_write			= native_apic_icr_write,

	.wait_icr_idle			= native_apic_wait_icr_idle,

	.safe_wait_icr_idle		= native_safe_apic_wait_icr_idle,

	.wait_icr_idle			= numachip_apic_wait_icr_idle,

	.safe_wait_icr_idle		= numachip_safe_apic_wait_icr_idle,

};

apic_driver(apic_numachip);



apic_driver(apic_numachip2);

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