Commit d2b78fb6 authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Gregory CLEMENT
Browse files

arm64: dts: marvell: update Armada AP806 clock description 



Following the review from the DT maintainers, the DT binding for the
clocks has changed, and we now use a DFX server node exposing a
syscon, with the clock nodes being subnodes of the DFX server
node. This commit therefore updates the AP806 Device Tree file to use
this new DT binding.

[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent ec7e5a56

arch/arm64/boot/dts/marvell/armada-ap806.dtsi

+20 −17
Original line number Original line Diff line number Diff line
@@ -179,23 +179,6 @@ 




			};

			};





			coreclk: clk@0x6F8204 {

				compatible = "marvell,armada-ap806-core-clock";

				reg = <0x6F8204 0x04>;

				#clock-cells = <1>;

				clock-output-names = "ddr", "ring", "cpu";

			};



			ringclk: clk@0x6F8250 {

				compatible = "marvell,armada-ap806-ring-clock";

				reg = <0x6F8250 0x04>;

				#clock-cells = <1>;

				clock-output-names = "ring-0", "ring-2",

						     "ring-3", "ring-4",

						     "ring-5";

				clocks = <&coreclk 1>;

			};



			xor0@400000 {

			xor0@400000 {

				compatible = "marvell,mv-xor-v2";

				compatible = "marvell,mv-xor-v2";

				reg = <0x400000 0x1000>,

				reg = <0x400000 0x1000>,
@@ -227,6 +210,26 @@ 
				msi-parent = <&gic_v2m0>;

				msi-parent = <&gic_v2m0>;

				dma-coherent;

				dma-coherent;

			};

			};



			dfx-server@6f8000 {

				compatible = "simple-mfd", "syscon";

				reg = <0x6f8000 0x70000>;



				coreclk: clk@204 {

					compatible = "marvell,armada-ap806-core-clock";

					#clock-cells = <1>;

					clock-output-names = "ddr", "ring", "cpu";

				};



				ringclk: clk@250 {

					compatible = "marvell,armada-ap806-ring-clock";

					#clock-cells = <1>;

					clock-output-names = "ring-0", "ring-2",

							     "ring-3", "ring-4",

							     "ring-5";

					clocks = <&coreclk 1>;

				};

			};

		};

		};

	};

	};

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