MIPS: define ioremap_nocache to ioremap

 */

#define ioremap(offset, size)						\

	__ioremap_mode((offset), (size), _CACHE_UNCACHED)

/*

 * ioremap_nocache     -   map bus memory into CPU space

 * @offset:    bus address of the memory

 * @size:      size of the resource to map

 *

 * ioremap_nocache performs a platform specific sequence of operations to

 * make bus memory CPU accessible via the readb/readw/readl/writeb/

 * writew/writel functions and the other mmio helpers. The returned

 * address is not guaranteed to be usable directly as a virtual

 * address.

 *

 * This version of ioremap ensures that the memory is marked uncachable

 * on the CPU as well as honouring existing caching rules from things like

 * the PCI bus. Note that there are other caches and buffers on many

 * busses. In particular driver authors should read up on PCI writes

 *

 * It's useful if some control registers are in such an area and

 * write combining or read caching is not desirable:

 */

#define ioremap_nocache(offset, size)					\

	__ioremap_mode((offset), (size), _CACHE_UNCACHED)

#define ioremap_uc ioremap_nocache

#define ioremap_nocache		ioremap

#define ioremap_uc		ioremap

/*

 * ioremap_cache -	map bus memory into CPU space