Commit d2283cdc authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'irq-urgent-2020-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq fixes from Thomas Gleixner:
 "A set of fixes for interrupt chip drivers:

   - Revert the platform driver conversion of interrupt chip drivers as
     it turned out to create more problems than it solves.

   - Fix a trivial typo in the new module helpers which made probing
     reliably fail.

   - Small fixes in the STM32 and MIPS Ingenic drivers

   - The TI firmware rework which had badly managed dependencies and had
     to wait post rc1"

* tag 'irq-urgent-2020-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/ingenic: Leave parent IRQ unmasked on suspend
  irqchip/stm32-exti: Avoid losing interrupts due to clearing pending bits by mistake
  irqchip: Revert modular support for drivers using IRQCHIP_PLATFORM_DRIVER helperse
  irqchip: Fix probing deferal when using IRQCHIP_PLATFORM_DRIVER helpers
  arm64: dts: k3-am65: Update the RM resource types
  arm64: dts: k3-am65: ti-sci-inta/intr: Update to latest bindings
  arm64: dts: k3-j721e: ti-sci-inta/intr: Update to latest bindings
  irqchip/ti-sci-inta: Add support for INTA directly connecting to GIC
  irqchip/ti-sci-inta: Do not store TISCI device id in platform device id field
  dt-bindings: irqchip: Convert ti, sci-inta bindings to yaml
  dt-bindings: irqchip: ti, sci-inta: Update docs to support different parent.
  irqchip/ti-sci-intr: Add support for INTR being a parent to INTR
  dt-bindings: irqchip: Convert ti, sci-intr bindings to yaml
  dt-bindings: irqchip: ti, sci-intr: Update bindings to drop the usage of gic as parent
  firmware: ti_sci: Add support for getting resource with subtype
  firmware: ti_sci: Drop unused structure ti_sci_rm_type_map
  firmware: ti_sci: Drop the device id to resource type translation
parents 0063a82d ceb2465c

Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt

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Texas Instruments K3 Interrupt Aggregator

=========================================



The Interrupt Aggregator (INTA) provides a centralized machine

which handles the termination of system events to that they can

be coherently processed by the host(s) in the system. A maximum

of 64 events can be mapped to a single interrupt.





                              Interrupt Aggregator

                     +-----------------------------------------+

                     |      Intmap            VINT             |

                     | +--------------+  +------------+        |

            m ------>| | vint  | bit  |  | 0 |.....|63| vint0  |

               .     | +--------------+  +------------+        |       +------+

               .     |         .               .               |       | HOST |

Globalevents  ------>|         .               .               |------>| IRQ  |

               .     |         .               .               |       | CTRL |

               .     |         .               .               |       +------+

            n ------>| +--------------+  +------------+        |

                     | | vint  | bit  |  | 0 |.....|63| vintx  |

                     | +--------------+  +------------+        |

                     |                                         |

                     +-----------------------------------------+



Configuration of these Intmap registers that maps global events to vint is done

by a system controller (like the Device Memory and Security Controller on K3

AM654 SoC). Driver should request the system controller to get the range

of global events and vints assigned to the requesting host. Management

of these requested resources should be handled by driver and requests

system controller to map specific global event to vint, bit pair.



Communication between the host processor running an OS and the system

controller happens through a protocol called TI System Control Interface

(TISCI protocol). For more details refer:

Documentation/devicetree/bindings/arm/keystone/ti,sci.txt



TISCI Interrupt Aggregator Node:

-------------------------------

- compatible:		Must be "ti,sci-inta".

- reg:			Should contain registers location and length.

- interrupt-controller:	Identifies the node as an interrupt controller

- msi-controller:	Identifies the node as an MSI controller.

- interrupt-parent:	phandle of irq parent.

- ti,sci:		Phandle to TI-SCI compatible System controller node.

- ti,sci-dev-id:	TISCI device ID of the Interrupt Aggregator.

- ti,sci-rm-range-vint:	Array of TISCI subtype ids representing vints(inta

			outputs) range within this INTA, assigned to the

			requesting host context.

- ti,sci-rm-range-global-event:	Array of TISCI subtype ids representing the

			global events range reaching this IA and are assigned

			to the requesting host context.



Example:

--------

main_udmass_inta: interrupt-controller@33d00000 {

	compatible = "ti,sci-inta";

	reg = <0x0 0x33d00000 0x0 0x100000>;

	interrupt-controller;

	msi-controller;

	interrupt-parent = <&main_navss_intr>;

	ti,sci = <&dmsc>;

	ti,sci-dev-id = <179>;

	ti,sci-rm-range-vint = <0x0>;

	ti,sci-rm-range-global-event = <0x1>;

};

Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Texas Instruments K3 Interrupt Aggregator



maintainers:

  - Lokesh Vutla <lokeshvutla@ti.com>



allOf:

  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#



description: |

  The Interrupt Aggregator (INTA) provides a centralized machine

  which handles the termination of system events to that they can

  be coherently processed by the host(s) in the system. A maximum

  of 64 events can be mapped to a single interrupt.



                                Interrupt Aggregator

                       +-----------------------------------------+

                       |      Intmap            VINT             |

                       | +--------------+  +------------+        |

              m ------>| | vint  | bit  |  | 0 |.....|63| vint0  |

                 .     | +--------------+  +------------+        |      +------+

                 .     |         .               .               |      | HOST |

  Globalevents  ------>|         .               .               |----->| IRQ  |

                 .     |         .               .               |      | CTRL |

                 .     |         .               .               |      +------+

              n ------>| +--------------+  +------------+        |

                       | | vint  | bit  |  | 0 |.....|63| vintx  |

                       | +--------------+  +------------+        |

                       |                                         |

                       +-----------------------------------------+



  Configuration of these Intmap registers that maps global events to vint is

  done by a system controller (like the Device Memory and Security Controller

  on AM654 SoC). Driver should request the system controller to get the range

  of global events and vints assigned to the requesting host. Management

  of these requested resources should be handled by driver and requests

  system controller to map specific global event to vint, bit pair.



  Communication between the host processor running an OS and the system

  controller happens through a protocol called TI System Control Interface

  (TISCI protocol).



properties:

  compatible:

    const: ti,sci-inta



  reg:

    maxItems: 1



  interrupt-controller: true



  msi-controller: true



  ti,interrupt-ranges:

    $ref: /schemas/types.yaml#/definitions/uint32-matrix

    description: |

      Interrupt ranges that converts the INTA output hw irq numbers

      to parents's input interrupt numbers.

    items:

      items:

        - description: |

            "output_irq" specifies the base for inta output irq

        - description: |

            "parent's input irq" specifies the base for parent irq

        - description: |

            "limit" specifies the limit for translation



required:

  - compatible

  - reg

  - interrupt-controller

  - msi-controller

  - ti,sci

  - ti,sci-dev-id

  - ti,interrupt-ranges



examples:

  - |

    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        main_udmass_inta: msi-controller@33d00000 {

            compatible = "ti,sci-inta";

            reg = <0x0 0x33d00000 0x0 0x100000>;

            interrupt-controller;

            msi-controller;

            interrupt-parent = <&main_navss_intr>;

            ti,sci = <&dmsc>;

            ti,sci-dev-id = <179>;

            ti,interrupt-ranges = <0 0 256>;

        };

    };

Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt

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Texas Instruments K3 Interrupt Router

=====================================



The Interrupt Router (INTR) module provides a mechanism to mux M

interrupt inputs to N interrupt outputs, where all M inputs are selectable

to be driven per N output. An Interrupt Router can either handle edge triggered

or level triggered interrupts and that is fixed in hardware.



                                 Interrupt Router

                             +----------------------+

                             |  Inputs     Outputs  |

        +-------+            | +------+    +-----+  |

        | GPIO  |----------->| | irq0 |    |  0  |  |       Host IRQ

        +-------+            | +------+    +-----+  |      controller

                             |    .           .     |      +-------+

        +-------+            |    .           .     |----->|  IRQ  |

        | INTA  |----------->|    .           .     |      +-------+

        +-------+            |    .        +-----+  |

                             | +------+    |  N  |  |

                             | | irqM |    +-----+  |

                             | +------+             |

                             |                      |

                             +----------------------+



There is one register per output (MUXCNTL_N) that controls the selection.

Configuration of these MUXCNTL_N registers is done by a system controller

(like the Device Memory and Security Controller on K3 AM654 SoC). System

controller will keep track of the used and unused registers within the Router.

Driver should request the system controller to get the range of GIC IRQs

assigned to the requesting hosts. It is the drivers responsibility to keep

track of Host IRQs.



Communication between the host processor running an OS and the system

controller happens through a protocol called TI System Control Interface

(TISCI protocol). For more details refer:

Documentation/devicetree/bindings/arm/keystone/ti,sci.txt



TISCI Interrupt Router Node:

----------------------------

Required Properties:

- compatible:		Must be "ti,sci-intr".

- ti,intr-trigger-type:	Should be one of the following:

			1: If intr supports edge triggered interrupts.

			4: If intr supports level triggered interrupts.

- interrupt-controller:	Identifies the node as an interrupt controller

- #interrupt-cells:	Specifies the number of cells needed to encode an

			interrupt source. The value should be 2.

			First cell should contain the TISCI device ID of source

			Second cell should contain the interrupt source offset

			within the device.

- ti,sci:		Phandle to TI-SCI compatible System controller node.

- ti,sci-dst-id:	TISCI device ID of the destination IRQ controller.

- ti,sci-rm-range-girq:	Array of TISCI subtype ids representing the host irqs

			assigned to this interrupt router. Each subtype id

			corresponds to a range of host irqs.



For more details on TISCI IRQ resource management refer:

https://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html



Example:

--------

The following example demonstrates both interrupt router node and the consumer

node(main gpio) on the AM654 SoC:



main_intr: interrupt-controller0 {

	compatible = "ti,sci-intr";

	ti,intr-trigger-type = <1>;

	interrupt-controller;

	interrupt-parent = <&gic500>;

	#interrupt-cells = <2>;

	ti,sci = <&dmsc>;

	ti,sci-dst-id = <56>;

	ti,sci-rm-range-girq = <0x1>;

};



main_gpio0: gpio@600000 {

	...

	interrupt-parent = <&main_intr>;

	interrupts = <57 256>, <57 257>, <57 258>,

		     <57 259>, <57 260>, <57 261>;

	...

};

Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Texas Instruments K3 Interrupt Router



maintainers:

  - Lokesh Vutla <lokeshvutla@ti.com>



allOf:

  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#



description: |

  The Interrupt Router (INTR) module provides a mechanism to mux M

  interrupt inputs to N interrupt outputs, where all M inputs are selectable

  to be driven per N output. An Interrupt Router can either handle edge

  triggered or level triggered interrupts and that is fixed in hardware.



                                   Interrupt Router

                               +----------------------+

                               |  Inputs     Outputs  |

          +-------+            | +------+    +-----+  |

          | GPIO  |----------->| | irq0 |    |  0  |  |       Host IRQ

          +-------+            | +------+    +-----+  |      controller

                               |    .           .     |      +-------+

          +-------+            |    .           .     |----->|  IRQ  |

          | INTA  |----------->|    .           .     |      +-------+

          +-------+            |    .        +-----+  |

                               | +------+    |  N  |  |

                               | | irqM |    +-----+  |

                               | +------+             |

                               |                      |

                               +----------------------+



  There is one register per output (MUXCNTL_N) that controls the selection.

  Configuration of these MUXCNTL_N registers is done by a system controller

  (like the Device Memory and Security Controller on K3 AM654 SoC). System

  controller will keep track of the used and unused registers within the Router.

  Driver should request the system controller to get the range of GIC IRQs

  assigned to the requesting hosts. It is the drivers responsibility to keep

  track of Host IRQs.



  Communication between the host processor running an OS and the system

  controller happens through a protocol called TI System Control Interface

  (TISCI protocol).



properties:

  compatible:

    const: ti,sci-intr



  ti,intr-trigger-type:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [1, 4]

    description: |

      Should be one of the following.

        1 = If intr supports edge triggered interrupts.

        4 = If intr supports level triggered interrupts.



  interrupt-controller: true



  '#interrupt-cells':

    const: 1

    description: |

      The 1st cell should contain interrupt router input hw number.



  ti,interrupt-ranges:

    $ref: /schemas/types.yaml#/definitions/uint32-matrix

    description: |

      Interrupt ranges that converts the INTR output hw irq numbers

      to parents's input interrupt numbers.

    items:

      items:

        - description: |

            "output_irq" specifies the base for intr output irq

        - description: |

            "parent's input irq" specifies the base for parent irq

        - description: |

            "limit" specifies the limit for translation



required:

  - compatible

  - ti,intr-trigger-type

  - interrupt-controller

  - '#interrupt-cells'

  - ti,sci

  - ti,sci-dev-id

  - ti,interrupt-ranges



examples:

  - |

    main_gpio_intr: interrupt-controller0 {

        compatible = "ti,sci-intr";

        ti,intr-trigger-type = <1>;

        interrupt-controller;

        interrupt-parent = <&gic500>;

        #interrupt-cells = <1>;

        ti,sci = <&dmsc>;

        ti,sci-dev-id = <131>;

        ti,interrupt-ranges = <0 360 32>;

    };

MAINTAINERS

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@@ -17117,8 +17117,8 @@ S: Maintained 
F:	Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml

F:	Documentation/devicetree/bindings/arm/keystone/ti,sci.txt

F:	Documentation/devicetree/bindings/clock/ti,sci-clk.txt

F:	Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt

F:	Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt

F:	Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml

F:	Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml

F:	Documentation/devicetree/bindings/reset/ti,sci-reset.txt

F:	Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt

F:	drivers/clk/keystone/sci-clk.c

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