Commit d1dcb05f authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/include: Add OCSC registers 



Add registers for handling Post Gamma Color Blending (OCSC), which is
useful for conversion from RGB->YUV for HDMI.

Reviewed-by: default avatarLeo Li <sunpeng.li@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9e3e90c5

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h

+4 −0
Original line number Diff line number Diff line
@@ -8134,6 +8134,10 @@ 
#define mmMPC_OUT5_CSC_C33_C34_B                                                                       0x1604

#define mmMPC_OUT5_CSC_C33_C34_B_BASE_IDX                                                              2









#define mmMPC_OCSC_TEST_DEBUG_INDEX                                                                    0x163b









#define mmMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX                                                           2









#define mmMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX                                                            2









#define mmMPC_OCSC_TEST_DEBUG_DATA                                                                     0x163c

















// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec









// base address: 0x5964

























drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h



+8
−1






























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Diff line number
Diff line







@@ -28263,7 +28263,14 @@







#define MPC_OUT5_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10









#define MPC_OUT5_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL









#define MPC_OUT5_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L

















//MPC_OCSC_TEST_DEBUG_INDEX









#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX__SHIFT                                           0x0









#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN__SHIFT                                        0x8









#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX_MASK                                             0x000000FFL









#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN_MASK                                          0x00000100L









//MPC_OCSC_TEST_DEBUG_DATA









#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA__SHIFT                                             0x0









#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA_MASK                                               0xFFFFFFFFL

















// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec









//DC_PERFMON17_PERFCOUNTER_CNTL

























drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h



+4
−1






























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Diff line number
Diff line







@@ -7103,7 +7103,10 @@







#define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              2









#define mmMPC_OUT3_CSC_C33_C34_B                                                                       0x15ea









#define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              2

















#define mmMPC_OCSC_TEST_DEBUG_INDEX                                                                    0x163b









#define mmMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX                                                           2









#define mmMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX                                                            2









#define mmMPC_OCSC_TEST_DEBUG_DATA                                                                     0x163c

















// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec









// base address: 0x5964

























drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h



+8
−0






























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Diff line number
Diff line







@@ -56634,5 +56634,13 @@







#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L









#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L

















//MPC_OCSC_TEST_DEBUG_INDEX









#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX__SHIFT                                           0x0









#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN__SHIFT                                        0x8









#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX_MASK                                             0x000000FFL









#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN_MASK                                          0x00000100L









//MPC_OCSC_TEST_DEBUG_DATA









#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA__SHIFT                                             0x0









#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA_MASK                                               0xFFFFFFFFL

















#endif



























































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