Unverified Commit d1af2ab3 authored by Paul Burton's avatar Paul Burton
Browse files

MIPS: Disable pte_special() for MIPS32 with RiXi 



Commit 61cbfff4 ("MIPS: pte_special()/pte_mkspecial() support")
added a _PAGE_SPECIAL bit to the pgprot bits of our PTEs. Unfortunately
for MIPS32 configurations with RiXi support this pushed the number of
pgprot bits to 13. Since the PFN field in EntryLo begins at bit 12 this
results in us shifting the most significant bit of the physical address
beyond the end of the PTE, leading any mapped access to a physical
address above 2GB to incorrectly access an address 2GB lower than
intended.

For now, disable the pte_special() support for MIPS32 configurations
that support RiXi.

Fixes: 61cbfff4 ("MIPS: pte_special()/pte_mkspecial() support")
Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: Dmitry Korotin <dkorotin@wavecomp.com>
Cc: linux-mips@vger.kernel.org
parent c4d48cf5

arch/mips/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ config MIPS 
	select RTC_LIB

	select SYSCTL_EXCEPTION_TRACE

	select VIRT_TO_BUS

	select ARCH_HAS_PTE_SPECIAL

	select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)



menu "Machine selection"

arch/mips/include/asm/pgtable-bits.h

+13 −1
Original line number Diff line number Diff line
@@ -52,7 +52,9 @@ enum pgtable_bits { 
	_PAGE_WRITE_SHIFT,

	_PAGE_ACCESSED_SHIFT,

	_PAGE_MODIFIED_SHIFT,

#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)

	_PAGE_SPECIAL_SHIFT,

#endif

};



/*
@@ -79,7 +81,9 @@ enum pgtable_bits { 
	_PAGE_WRITE_SHIFT,

	_PAGE_ACCESSED_SHIFT,

	_PAGE_MODIFIED_SHIFT,

#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)

	_PAGE_SPECIAL_SHIFT,

#endif

};



#elif defined(CONFIG_CPU_R3K_TLB)
@@ -92,7 +96,9 @@ enum pgtable_bits { 
	_PAGE_WRITE_SHIFT,

	_PAGE_ACCESSED_SHIFT,

	_PAGE_MODIFIED_SHIFT,

#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)

	_PAGE_SPECIAL_SHIFT,

#endif



	/* Used by TLB hardware (placed in EntryLo) */

	_PAGE_GLOBAL_SHIFT = 8,
@@ -116,7 +122,9 @@ enum pgtable_bits { 
#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)

	_PAGE_HUGE_SHIFT,

#endif

#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)

	_PAGE_SPECIAL_SHIFT,

#endif



	/* Used by TLB hardware (placed in EntryLo*) */

#if defined(CONFIG_CPU_HAS_RIXI)
@@ -139,7 +147,11 @@ enum pgtable_bits { 
#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)

# define _PAGE_HUGE		(1 << _PAGE_HUGE_SHIFT)

#endif

#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)

# define _PAGE_SPECIAL		(1 << _PAGE_SPECIAL_SHIFT)

#else

# define _PAGE_SPECIAL		0

#endif



/* Used by TLB hardware (placed in EntryLo*) */

#if defined(CONFIG_XPA)

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