Commit d191aaff authored Mar 25, 2020 by Huacai Chen Committed by Thomas Bogendoerfer Mar 25, 2020

MIPS/tlbex: Fix LDDIR usage in setup_pw() for Loongson-3



LDDIR/LDPTE is Loongson-3's acceleration for Page Table Walking. If BD
(Base Directory, the 4th page directory) is not enabled, then GDOffset
is biased by BadVAddr[63:62]. So, if GDOffset (aka. BadVAddr[47:36] for
Loongson-3) is big enough, "0b11(BadVAddr[63:62])|BadVAddr[47:36]|...."
can far beyond pg_swapper_dir. This means the pg_swapper_dir may NOT be
accessed by LDDIR correctly, so fix it by set PWDirExt in CP0_PWCtl.

Cc: <stable@vger.kernel.org>
Signed-off-by: Pei Huang <huangpei@loongson.cn>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

parent 78bdbbac

arch/mips/mm/tlbex.c

+4 −1

Original line number	Diff line number	Diff line
		@@ -1480,6 +1480,7 @@ static void build_r4000_tlb_refill_handler(void)

		static void setup_pw(void)
		{
		unsigned int pwctl;
		unsigned long pgd_i, pgd_w;
		#ifndef __PAGETABLE_PMD_FOLDED
		unsigned long pmd_i, pmd_w;
		@@ -1506,6 +1507,7 @@ static void setup_pw(void)

		pte_i = ilog2(_PAGE_GLOBAL);
		pte_w = 0;
		pwctl = 1 << 30; /* Set PWDirExt */

		#ifndef __PAGETABLE_PMD_FOLDED
		write_c0_pwfield(pgd_i << 24 \| pmd_i << 12 \| pt_i << 6 \| pte_i);
		@@ -1516,8 +1518,9 @@ static void setup_pw(void)
		#endif

		#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
		write_c0_pwctl(1 << 6 \| psn);
		pwctl \|= (1 << 6 \| psn);
		#endif
		write_c0_pwctl(pwctl);
		write_c0_kpgd((long)swapper_pg_dir);
		kscratch_used_mask \|= (1 << 7); /* KScratch6 is used for KPGD */
		}

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