Commit d18edcb2 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
Browse files

[TG3]: Exit irq handler during chip reset. 



On most tg3 chips, the memory enable bit in the PCI command register
gets cleared during chip reset and must be restored before accessing
PCI registers using memory cycles.  The chip does not generate
interrupt during chip reset, but the irq handler can still be called
because of irq sharing or irqpoll.  Reading a register in the irq
handler can cause a master abort in this scenario and may result in a
crash on some architectures.

Use the TG3_FLAG_CHIP_RESETTING flag to tell the irq handler to exit
without touching any registers.  The checking of the flag is in the
"slow" path of the irq handler and will not affect normal performance.
The msi handler is not shared and therefore does not require checking
the flag.

Thanks to Bernhard Walle <bwalle@suse.de> for reporting the problem.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 1c46ae05

drivers/net/tg3.c

+66 −47
Original line number Diff line number Diff line
@@ -3568,8 +3568,14 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id) 
	 * Reading the PCI State register will confirm whether the

	 * interrupt is ours and will flush the status block.

	 */

	if ((sblk->status & SD_STATUS_UPDATED) ||

	    !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {

	if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {

		if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||

		    (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {

			handled = 0;

			goto out;

		}

	}



	/*

	 * Writing any value to intr-mbox-0 clears PCI INTA# and

	 * chip-internal interrupt pending events.
@@ -3577,8 +3583,7 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id) 
	 * NIC to stop sending us irqs, engaging "in-intr-handler"

	 * event coalescing.

	 */

		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,

			     0x00000001);

	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);

	if (tg3_irq_sync(tp))

		goto out;

	sblk->status &= ~SD_STATUS_UPDATED;
@@ -3592,9 +3597,6 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id) 
		tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,

			       0x00000000);

	}

	} else {	/* shared interrupt */

		handled = 0;

	}

out:

	return IRQ_RETVAL(handled);

}
@@ -3611,8 +3613,14 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) 
	 * Reading the PCI State register will confirm whether the

	 * interrupt is ours and will flush the status block.

	 */

	if ((sblk->status_tag != tp->last_tag) ||

	    !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {

	if (unlikely(sblk->status_tag == tp->last_tag)) {

		if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||

		    (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {

			handled = 0;

			goto out;

		}

	}



	/*

	 * writing any value to intr-mbox-0 clears PCI INTA# and

	 * chip-internal interrupt pending events.
@@ -3620,8 +3628,7 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) 
	 * NIC to stop sending us irqs, engaging "in-intr-handler"

	 * event coalescing.

	 */

		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,

			     0x00000001);

	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);

	if (tg3_irq_sync(tp))

		goto out;

	if (netif_rx_schedule_prep(dev)) {
@@ -3634,9 +3641,6 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) 
		tp->last_tag = sblk->status_tag;

		__netif_rx_schedule(dev);

	}

	} else {	/* shared interrupt */

		handled = 0;

	}

out:

	return IRQ_RETVAL(handled);

}
@@ -4823,6 +4827,19 @@ static int tg3_chip_reset(struct tg3 *tp) 
	if (write_op == tg3_write_flush_reg32)

		tp->write32 = tg3_write32;



	/* Prevent the irq handler from reading or writing PCI registers

	 * during chip reset when the memory enable bit in the PCI command

	 * register may be cleared.  The chip does not generate interrupt

	 * at this time, but the irq handler may still be called due to irq

	 * sharing or irqpoll.

	 */

	tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;

	tp->hw_status->status = 0;

	tp->hw_status->status_tag = 0;

	tp->last_tag = 0;

	smp_mb();

	synchronize_irq(tp->pdev->irq);



	/* do the reset */

	val = GRC_MISC_CFG_CORECLK_RESET;
@@ -4904,6 +4921,8 @@ static int tg3_chip_reset(struct tg3 *tp) 


	pci_restore_state(tp->pdev);



	tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;



	/* Make sure PCI-X relaxed ordering bit is clear. */

	pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);

	val &= ~PCIX_CAPS_RELAXED_ORDERING;

drivers/net/tg3.h

+1 −0
Original line number Diff line number Diff line
@@ -2223,6 +2223,7 @@ struct tg3 { 
#define TG3_FLAG_40BIT_DMA_BUG		0x08000000

#define TG3_FLAG_BROKEN_CHECKSUMS	0x10000000

#define TG3_FLAG_GOT_SERDES_FLOWCTL	0x20000000

#define TG3_FLAG_CHIP_RESETTING		0x40000000

#define TG3_FLAG_INIT_COMPLETE		0x80000000

	u32				tg3_flags2;

#define TG3_FLG2_RESTART_TIMER		0x00000001

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