Commit d16f0f61 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-fixes-5.5-2019-12-12' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 



drm-fixes-5.5-2019-12-12:

amdgpu:
- DC fixes for renoir
- Gfx8 fence flush align with mesa
- Power profile fix for arcturus
- Freesync fix
- DC I2c over aux fix
- DC aux defer fix
- GPU reset fix
- GPUVM invalidation semaphore fixes for PCO and SR-IOV
- Golden settings updates for gfx10

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191212223211.8034-1-alexander.deucher@amd.com
parents 82e50ec8 f271fe18

drivers/gpu/drm/amd/acp/Kconfig

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

# SPDX-License-Identifier: MIT

menu "ACP (Audio CoProcessor) Configuration"



config DRM_AMD_ACP

drivers/gpu/drm/amd/amdgpu/Kconfig

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

# SPDX-License-Identifier: MIT

config DRM_AMDGPU_SI

	bool "Enable amdgpu support for SI parts"

	depends on DRM_AMDGPU

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+1 −4
Original line number Diff line number Diff line
@@ -604,11 +604,8 @@ void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) 
			continue;

		}



		for (i = 0; i < num_entities; i++) {

			mutex_lock(&ctx->adev->lock_reset);

		for (i = 0; i < num_entities; i++)

			drm_sched_entity_fini(&ctx->entities[0][i].entity);

			mutex_unlock(&ctx->adev->lock_reset);

		}

	}

}

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

+22 −16
Original line number Diff line number Diff line
@@ -268,24 +268,30 @@ static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev, 
{

	u32 tmp;



	if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) {

		/* Put DF on broadcast mode */

		adev->df_funcs->enable_broadcast_mode(adev, true);



	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {

		tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

		if (enable) {

			tmp = RREG32_SOC15(DF, 0,

					mmDF_PIE_AON0_DfGlobalClkGater);

			tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;

			tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;

		WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);

			WREG32_SOC15(DF, 0,

					mmDF_PIE_AON0_DfGlobalClkGater, tmp);

		} else {

		tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

			tmp = RREG32_SOC15(DF, 0,

					mmDF_PIE_AON0_DfGlobalClkGater);

			tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;

			tmp |= DF_V3_6_MGCG_DISABLE;

		WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);

			WREG32_SOC15(DF, 0,

					mmDF_PIE_AON0_DfGlobalClkGater, tmp);

		}



		/* Exit broadcast mode */

		adev->df_funcs->enable_broadcast_mode(adev, false);

	}

}



static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,

					  u32 *flags)

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+6 −0
Original line number Diff line number Diff line
@@ -117,10 +117,13 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070104),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
@@ -162,10 +165,13 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070105),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),

CRA Git | Maintained and supported by SUSTech CRA and CCSE