Commit d15ae814 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-for-v4.7-rc8-intel-kbl' of git://people.freedesktop.org/~airlied/linux 

Pull intel kabylake drm fixes from Dave Airlie:
 "As mentioned Intel has gathered all the Kabylake fixes from -next,
  which we've enabled in 4.7 for the first time, these are pretty much
  limited in scope to only affects kabylake, which is hw that isn't
  shipping yet.  So I'm mostly okay with it going in now.

  If we don't land this, it might be a good idea to disable kabylake
  support in 4.7 before we ship"

* tag 'drm-fixes-for-v4.7-rc8-intel-kbl' of git://people.freedesktop.org/~airlied/linux: (28 commits)
  drm/i915/kbl: Introduce the first official DMC for Kabylake.
  drm/i915: Introduce Kabypoint PCH for Kabylake H/DT.
  drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate
  drm/i915/gen9: Add WaFbcHighMemBwCorruptionAvoidance
  drm/i195/fbc: Add WaFbcNukeOnHostModify
  drm/i915/gen9: Add WaFbcWakeMemOn
  drm/i915/gen9: Add WaFbcTurnOffFbcWatermark
  drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch
  drm/i915/gen9: Add WaEnableChickenDCPR
  drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
  drm/i915/kbl: Add WaDisableGafsUnitClkGating
  drm/i915/kbl: Add WaForGAMHang
  drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
  drm/i915/kbl: Add WaDisableDynamicCreditSharing
  drm/i915/kbl: Add WaDisableGamClockGating
  drm/i915/gen9: Enable must set chicken bits in config0 reg
  drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
  drm/i915/kbl: Add WaDisableSDEUnitClockGating
  drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
  drm/i915/kbl: Add WaEnableGapsTsvCreditFix
  ...
parents 3f2625d7 cad7d8d9

drivers/gpu/drm/i915/i915_drv.c

+4 −0
Original line number Diff line number Diff line
@@ -512,6 +512,10 @@ void intel_detect_pch(struct drm_device *dev) 
				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");

				WARN_ON(!IS_SKYLAKE(dev) &&

					!IS_KABYLAKE(dev));

			} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_KBP;

				DRM_DEBUG_KMS("Found KabyPoint PCH\n");

				WARN_ON(!IS_KABYLAKE(dev));

			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||

				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||

				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&

drivers/gpu/drm/i915/i915_drv.h

+12 −0
Original line number Diff line number Diff line
@@ -990,6 +990,7 @@ enum intel_pch { 
	PCH_CPT,	/* Cougarpoint PCH */

	PCH_LPT,	/* Lynxpoint PCH */

	PCH_SPT,        /* Sunrisepoint PCH */

	PCH_KBP,        /* Kabypoint PCH */

	PCH_NOP,

};
@@ -2600,6 +2601,15 @@ struct drm_i915_cmd_table { 


#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))



#define KBL_REVID_A0		0x0

#define KBL_REVID_B0		0x1

#define KBL_REVID_C0		0x2

#define KBL_REVID_D0		0x3

#define KBL_REVID_E0		0x4



#define IS_KBL_REVID(p, since, until) \

	(IS_KABYLAKE(p) && IS_REVID(p, since, until))



/*

 * The genX designation typically refers to the render engine, so render

 * capability related checks should use IS_GEN, while display and other checks
@@ -2708,11 +2718,13 @@ struct drm_i915_cmd_table { 
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00

#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100

#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00

#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200

#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100

#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000

#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */



#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)

#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)

#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)

#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)

#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)

drivers/gpu/drm/i915/i915_gem_stolen.c

+4 −2
Original line number Diff line number Diff line
@@ -55,8 +55,10 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, 
		return -ENODEV;



	/* See the comment at the drm_mm_init() call for more about this check.

	 * WaSkipStolenMemoryFirstPage:bdw,chv (incomplete) */

	if (INTEL_INFO(dev_priv)->gen == 8 && start < 4096)

	 * WaSkipStolenMemoryFirstPage:bdw,chv,kbl (incomplete)

	 */

	if (start < 4096 && (IS_GEN8(dev_priv) ||

			     IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)))

		start = 4096;



	mutex_lock(&dev_priv->mm.stolen_lock);

drivers/gpu/drm/i915/i915_irq.c

+2 −2
Original line number Diff line number Diff line
@@ -2471,7 +2471,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) 
			I915_WRITE(SDEIIR, iir);

			ret = IRQ_HANDLED;



			if (HAS_PCH_SPT(dev_priv))

			if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))

				spt_irq_handler(dev, iir);

			else

				cpt_irq_handler(dev, iir);
@@ -4661,7 +4661,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) 
		dev->driver->disable_vblank = gen8_disable_vblank;

		if (IS_BROXTON(dev))

			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;

		else if (HAS_PCH_SPT(dev))

		else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))

			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;

		else

			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;

drivers/gpu/drm/i915/i915_reg.h

+21 −0
Original line number Diff line number Diff line
@@ -220,6 +220,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)

#define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)



#define GEN8_CONFIG0			_MMIO(0xD00)

#define  GEN9_DEFAULT_FIXES		(1 << 3 | 1 << 2 | 1 << 1)



#define GAC_ECO_BITS			_MMIO(0x14090)

#define   ECOBITS_SNB_BIT		(1<<13)

#define   ECOBITS_PPGTT_CACHE64B	(3<<8)
@@ -1669,6 +1672,9 @@ enum skl_disp_power_wells { 


#define GEN7_TLB_RD_ADDR	_MMIO(0x4700)



#define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)

#define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1<<28)



#if 0

#define PRB0_TAIL	_MMIO(0x2030)

#define PRB0_HEAD	_MMIO(0x2034)
@@ -1804,6 +1810,10 @@ enum skl_disp_power_wells { 
#define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))

#define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))



/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */

#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)

#define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)



/* WaClearTdlStateAckDirtyBits */

#define GEN8_STATE_ACK		_MMIO(0x20F0)

#define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)
@@ -2200,6 +2210,8 @@ enum skl_disp_power_wells { 
#define ILK_DPFC_STATUS		_MMIO(0x43210)

#define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)

#define ILK_DPFC_CHICKEN	_MMIO(0x43224)

#define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)

#define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION	(1<<23)

#define ILK_FBC_RT_BASE		_MMIO(0x2128)

#define   ILK_FBC_RT_VALID	(1<<0)

#define   SNB_FBC_FRONT_BUFFER	(1<<1)
@@ -6031,6 +6043,7 @@ enum skl_disp_power_wells { 
#define CHICKEN_PAR1_1		_MMIO(0x42080)

#define  DPA_MASK_VBLANK_SRD	(1 << 15)

#define  FORCE_ARB_IDLE_PLANES	(1 << 14)

#define  SKL_EDP_PSR_FIX_RDWRAP	(1 << 3)



#define _CHICKEN_PIPESL_1_A	0x420b0

#define _CHICKEN_PIPESL_1_B	0x420b4
@@ -6039,6 +6052,7 @@ enum skl_disp_power_wells { 
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)



#define DISP_ARB_CTL	_MMIO(0x45000)

#define  DISP_FBC_MEMORY_WAKE		(1<<31)

#define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)

#define  DISP_FBC_WM_DIS		(1<<15)

#define DISP_ARB_CTL2	_MMIO(0x45004)
@@ -6052,6 +6066,9 @@ enum skl_disp_power_wells { 
#define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)

#define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)



#define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)

#define   MASK_WAKEMEM			(1<<13)



#define SKL_DFSM			_MMIO(0x51000)

#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)

#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
@@ -6069,6 +6086,7 @@ enum skl_disp_power_wells { 
#define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)



#define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)

#define GEN9_CTX_PREEMPT_REG		_MMIO(0x2248)

#define GEN8_CS_CHICKEN1		_MMIO(0x2580)



/* GEN7 chicken */
@@ -6076,6 +6094,7 @@ enum skl_disp_power_wells { 
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))

# define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)

#define COMMON_SLICE_CHICKEN2			_MMIO(0x7014)

# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)

# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)



#define HIZ_CHICKEN					_MMIO(0x7018)
@@ -6921,6 +6940,7 @@ enum skl_disp_power_wells { 
#define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)



#define GEN6_UCGCTL1				_MMIO(0x9400)

# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE		(1 << 22)

# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)

# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)

# define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
@@ -6937,6 +6957,7 @@ enum skl_disp_power_wells { 


#define GEN7_UCGCTL4				_MMIO(0x940c)

#define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)

#define  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE	(1<<14)



#define GEN6_RCGCTL1				_MMIO(0x9410)

#define GEN6_RCGCTL2				_MMIO(0x9414)

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