Merge remote-tracking branch 'asoc/topic/tegra' into asoc-next

NVIDIA Tegra30 AHUB (Audio Hub)

Required properties:

- compatible : "nvidia,tegra30-ahub"

- compatible : "nvidia,tegra30-ahub", "nvidia,tegra114-ahub", etc.

- reg : Should contain the register physical address and length for each of

  the AHUB's APBIF registers and the AHUB's own registers.

  the AHUB's register blocks.

  - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.

  - Tegra114 requires an additional entry, for the APBIF2 register block.

- interrupts : Should contain AHUB interrupt

- nvidia,dma-request-selector : The Tegra DMA controller's phandle and

  request selector for the first APBIF channel.

- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each

  entry contains the Tegra DMA controller's phandle and request selector.

  If a single entry is present, the request selectors for the channels are

  assumed to be contiguous, and increment from this value.

  If multiple values are given, one value must be given per channel.

- clocks : Must contain an entry for each required entry in clock-names.

- clock-names : Must include the following entries:

  - Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0,

    dam1, dam2, spdif_in.

  - Tegra114: Additionally requires amx, adx.

- ranges : The bus address mapping for the configlink register bus.

  Can be empty since the mapping is 1:1.

- #address-cells : For the configlink bus. Should be <1>;

	reg = <0x70080000 0x200 0x70080200 0x100>;

	interrupts = < 0 103 0x04 >;

	nvidia,dma-request-selector = <&apbdma 1>;

	clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,

		<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,

		<&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,

		<&tegra_car 110>, <&tegra_car 162>;

	clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",

		"i2s3", "i2s4", "dam0", "dam1", "dam2",

		"spdif_in";

	ranges;

	#address-cells = <1>;

	#size-cells = <1>;

/*

 * Copyright 2011 NVIDIA, Inc.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and

 * may be copied, distributed, and modified under those terms.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */

#ifndef __SOUND_TEGRA_WM38903_H

#define __SOUND_TEGRA_WM38903_H

struct tegra_wm8903_platform_data {

	int gpio_spkr_en;

	int gpio_hp_det;

	int gpio_hp_mute;

	int gpio_int_mic_en;

	int gpio_ext_mic_en;

};

#endif

}

EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);

static const char * const configlink_clocks[] = {

	"i2s0",

	"i2s1",

	"i2s2",

	"i2s3",

	"i2s4",

	"dam0",

	"dam1",

	"dam2",

	"spdif_in",

#define CLK_LIST_MASK_TEGRA30	BIT(0)

#define CLK_LIST_MASK_TEGRA114	BIT(1)

#define CLK_LIST_MASK_TEGRA30_OR_LATER \

		(CLK_LIST_MASK_TEGRA30 | CLK_LIST_MASK_TEGRA114)

static const struct {

	const char *clk_name;

	u32 clk_list_mask;

} configlink_clocks[] = {

	{ "i2s0", CLK_LIST_MASK_TEGRA30_OR_LATER },

	{ "i2s1", CLK_LIST_MASK_TEGRA30_OR_LATER },

	{ "i2s2", CLK_LIST_MASK_TEGRA30_OR_LATER },

	{ "i2s3", CLK_LIST_MASK_TEGRA30_OR_LATER },

	{ "i2s4", CLK_LIST_MASK_TEGRA30_OR_LATER },

	{ "dam0", CLK_LIST_MASK_TEGRA30_OR_LATER },

	{ "dam1", CLK_LIST_MASK_TEGRA30_OR_LATER },

	{ "dam2", CLK_LIST_MASK_TEGRA30_OR_LATER },

	{ "spdif_in", CLK_LIST_MASK_TEGRA30_OR_LATER },

	{ "amx", CLK_LIST_MASK_TEGRA114 },

	{ "adx", CLK_LIST_MASK_TEGRA114 },

};

#define LAST_REG(name) \

	.cache_type = REGCACHE_RBTREE,

};

static struct tegra30_ahub_soc_data soc_data_tegra30 = {

	.clk_list_mask = CLK_LIST_MASK_TEGRA30,

};

static struct tegra30_ahub_soc_data soc_data_tegra114 = {

	.clk_list_mask = CLK_LIST_MASK_TEGRA114,

};

static const struct of_device_id tegra30_ahub_of_match[] = {

	{ .compatible = "nvidia,tegra114-ahub", .data = &soc_data_tegra114 },

	{ .compatible = "nvidia,tegra30-ahub",  .data = &soc_data_tegra30 },

	{},

};

static int tegra30_ahub_probe(struct platform_device *pdev)

{

	const struct of_device_id *match;

	const struct tegra30_ahub_soc_data *soc_data;

	struct clk *clk;

	int i;

	struct resource *res0, *res1, *region;

	if (ahub)

		return -ENODEV;

	match = of_match_device(tegra30_ahub_of_match, &pdev->dev);

	if (!match)

		return -EINVAL;

	soc_data = match->data;

	/*

	 * The AHUB hosts a register bus: the "configlink". For this to

	 * operate correctly, all devices on this bus must be out of reset.

	 * Ensure that here.

	 */

	for (i = 0; i < ARRAY_SIZE(configlink_clocks); i++) {

		clk = clk_get(&pdev->dev, configlink_clocks[i]);

		if (!(configlink_clocks[i].clk_list_mask &

					soc_data->clk_list_mask))

			continue;

		clk = clk_get(&pdev->dev, configlink_clocks[i].clk_name);

		if (IS_ERR(clk)) {

			dev_err(&pdev->dev, "Can't get clock %s\n",

				configlink_clocks[i]);

				configlink_clocks[i].clk_name);

			ret = PTR_ERR(clk);

			goto err;

		}

	return 0;

}

static const struct of_device_id tegra30_ahub_of_match[] = {

	{ .compatible = "nvidia,tegra30-ahub", },

	{},

};

static const struct dev_pm_ops tegra30_ahub_pm_ops = {

	SET_RUNTIME_PM_OPS(tegra30_ahub_runtime_suspend,

			   tegra30_ahub_runtime_resume, NULL)

					  enum tegra30_ahub_txcif txcif);

extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif);

struct tegra30_ahub_soc_data {

	u32 clk_list_mask;

	/*

	 * FIXME: There are many more differences in HW, such as:

	 * - More APBIF channels.

	 * - Extra separate chunks of register address space to represent

	 *   the extra APBIF channels.

	 * - More units connected to the AHUB, so that tegra30_ahub_[rt]xcif

	 *   need expansion, coupled with there being more defined bits in

	 *   the AHUB routing registers.

	 * However, the driver doesn't support those new features yet, so we

	 * don't represent them here yet.

	 */

};

struct tegra30_ahub {

	const struct tegra30_ahub_soc_data *soc_data;

	struct device *dev;

	struct clk *clk_d_audio;

	struct clk *clk_apbif;

			sizeof(struct tegra_alc5632), GFP_KERNEL);

	if (!alc5632) {

		dev_err(&pdev->dev, "Can't allocate tegra_alc5632\n");

		ret = -ENOMEM;

		goto err;

		return -ENOMEM;

	}

	card->dev = &pdev->dev;

	platform_set_drvdata(pdev, card);

	snd_soc_card_set_drvdata(card, alc5632);

	if (!(pdev->dev.of_node)) {

		dev_err(&pdev->dev, "Must be instantiated using device tree\n");

		ret = -EINVAL;

		goto err;

	}

	alc5632->gpio_hp_det = of_get_named_gpio(np, "nvidia,hp-det-gpios", 0);

	if (alc5632->gpio_hp_det == -EPROBE_DEFER)

		return -EPROBE_DEFER;

		goto err;

	}

	tegra_alc5632_dai.cpu_of_node = of_parse_phandle(

			pdev->dev.of_node, "nvidia,i2s-controller", 0);

	tegra_alc5632_dai.cpu_of_node = of_parse_phandle(np,

			"nvidia,i2s-controller", 0);

	if (!tegra_alc5632_dai.cpu_of_node) {

		dev_err(&pdev->dev,

			"Property 'nvidia,i2s-controller' missing or invalid\n");