Commit d14740fe authored Jul 04, 2016 by James Hogan Committed by Paolo Bonzini Jul 05, 2016

MIPS: KVM: Fix fpu.S misassembly with r6



__kvm_save_fpu and __kvm_restore_fpu use .set mips64r2 so that they can
access the odd FPU registers as well as the even, however this causes
misassembly of the return instruction on MIPSr6.

Fix by replacing .set mips64r2 with .set fp=64, which doesn't change the
architecture revision.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim KrÄmÃ¡Å™ <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

parent 1b492600

arch/mips/kvm/fpu.S

+5 −2

Original line number	Diff line number	Diff line
		@@ -14,13 +14,16 @@
		#include <asm/mipsregs.h>
		#include <asm/regdef.h>

		/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
		#undef fp

		.set noreorder
		.set noat

		LEAF(__kvm_save_fpu)
		.set push
		.set mips64r2
		SET_HARDFLOAT
		.set fp=64
		mfc0 t0, CP0_STATUS
		sll t0, t0, 5 # is Status.FR set?
		bgez t0, 1f # no: skip odd doubles
		@@ -63,8 +66,8 @@ LEAF(__kvm_save_fpu)

		LEAF(__kvm_restore_fpu)
		.set push
		.set mips64r2
		SET_HARDFLOAT
		.set fp=64
		mfc0 t0, CP0_STATUS
		sll t0, t0, 5 # is Status.FR set?
		bgez t0, 1f # no: skip odd doubles

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