net/mlx5e: CT: Expand tunnel register mappings (d12f4521) · Commits · 戴 / test

Reg_c1 is 32 bits wide. Originally, 24 bit were allocated for the tuple_id, 6 bits for tunnel mapping and 2 bits for tunnel options mappings. Restoring the ct state from zone lookup instead of tuple id requires reg_c1 to store 8 bits mapping the ct zone, leaving 24 bits for tunnel mappings. Expand tunnel and tunnel options register mappings to 12 bit each. Signed-off-by:

Paul Blakey <paulb@mellanox.com> Reviewed-by:

Oz Shlomo <ozsh@mellanox.com> Signed-off-by:

Saeed Mahameed <saeedm@mellanox.com>

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -180,8 +180,8 @@ struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
		},
		[TUNNEL_TO_REG] = {
		.mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
		.moffset = 3,
		.mlen = 1,
		.moffset = 1,
		.mlen = 3,
		.soffset = MLX5_BYTE_OFF(fte_match_param,
		misc_parameters_2.metadata_reg_c_1),
		},

drivers/net/ethernet/mellanox/mlx5/core/en_tc.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -70,9 +70,9 @@ struct tunnel_match_enc_opts {
		* Upper TUNNEL_INFO_BITS for general tunnel info.
		* Lower ENC_OPTS_BITS bits for enc_opts.
		*/
		#define TUNNEL_INFO_BITS 6
		#define TUNNEL_INFO_BITS 12
		#define TUNNEL_INFO_BITS_MASK GENMASK(TUNNEL_INFO_BITS - 1, 0)
		#define ENC_OPTS_BITS 2
		#define ENC_OPTS_BITS 12
		#define ENC_OPTS_BITS_MASK GENMASK(ENC_OPTS_BITS - 1, 0)
		#define TUNNEL_ID_BITS (TUNNEL_INFO_BITS + ENC_OPTS_BITS)
		#define TUNNEL_ID_MASK GENMASK(TUNNEL_ID_BITS - 1, 0)

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