Commit d114a139 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/flcn/msgq: move handling of init message to subdevs 



When the PMU/SEC2 LS FWs have booted, they'll send a message to the host
with various information, including the configuration of message/command
queues that are available.

Move the handling for this to the relevant subdevs.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 2d063981

drivers/gpu/drm/nouveau/include/nvfw/pmu.h

+31 −0
Original line number Diff line number Diff line 
#ifndef __NVFW_PMU_H__

#define __NVFW_PMU_H__



#define NV_PMU_UNIT_INIT                                                   0x07

#define NV_PMU_UNIT_ACR                                                    0x0a



struct nv_pmu_init_msg {

	struct nv_falcon_msg hdr;

#define NV_PMU_INIT_MSG_INIT                                               0x00

	u8 msg_type;



	u8 pad;

	u16 os_debug_entry_point;



	struct {

		u16 size;

		u16 offset;

		u8 index;

		u8 pad;

	} queue_info[5];



	u16 sw_managed_area_offset;

	u16 sw_managed_area_size;

};



struct nv_pmu_acr_cmd {

	struct nv_falcon_cmd hdr;

#define NV_PMU_ACR_CMD_INIT_WPR_REGION                                     0x00
@@ -16,6 +36,17 @@ struct nv_pmu_acr_msg { 
	u8 msg_type;

};



struct nv_pmu_acr_init_wpr_region_cmd {

	struct nv_pmu_acr_cmd cmd;

	u32 region_id;

	u32 wpr_offset;

};



struct nv_pmu_acr_init_wpr_region_msg {

	struct nv_pmu_acr_msg msg;

	u32 error_code;

};



struct nv_pmu_acr_bootstrap_falcon_cmd {

	struct nv_pmu_acr_cmd cmd;

#define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES                  0x00000000

drivers/gpu/drm/nouveau/include/nvfw/sec2.h

+22 −0
Original line number Diff line number Diff line 
#ifndef __NVFW_SEC2_H__

#define __NVFW_SEC2_H__



#define NV_SEC2_UNIT_INIT                                                  0x01

#define NV_SEC2_UNIT_ACR                                                   0x08



struct nv_sec2_init_msg {

	struct nv_falcon_msg hdr;

#define NV_SEC2_INIT_MSG_INIT                                              0x00

	u8 msg_type;



	u8 num_queues;

	u16 os_debug_entry_point;



	struct {

		u32 offset;

		u16 size;

		u8 index;

#define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ                                     0x00

#define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ                                     0x01

		u8 id;

	} queue_info[2];



	u32 sw_managed_area_offset;

	u16 sw_managed_area_size;

};



struct nv_sec2_acr_cmd {

	struct nv_falcon_cmd hdr;

#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON                                   0x00

drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h

+1 −0
Original line number Diff line number Diff line
@@ -72,4 +72,5 @@ int nvkm_falcon_msgq_new(struct nvkm_falcon_qmgr *, const char *name, 
void nvkm_falcon_msgq_del(struct nvkm_falcon_msgq **);

void nvkm_falcon_msgq_init(struct nvkm_falcon_msgq *,

			   u32 index, u32 offset, u32 size);

int nvkm_falcon_msgq_recv_initmsg(struct nvkm_falcon_msgq *, void *, u32 size);

#endif

drivers/gpu/drm/nouveau/include/nvkm/core/msgqueue.h

+0 −1
Original line number Diff line number Diff line
@@ -32,7 +32,6 @@ int nvkm_msgqueue_new(u32, struct nvkm_falcon *, const struct nvkm_secboot *, 
		      struct nvkm_msgqueue **);

void nvkm_msgqueue_del(struct nvkm_msgqueue **);

void nvkm_msgqueue_recv(struct nvkm_msgqueue *);

int nvkm_msgqueue_reinit(struct nvkm_msgqueue *);



/* useful if we run a NVIDIA-signed firmware */

void nvkm_msgqueue_write_cmdline(struct nvkm_msgqueue *, void *);

drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h

+2 −0
Original line number Diff line number Diff line
@@ -14,7 +14,9 @@ struct nvkm_sec2 { 
	struct nvkm_falcon_cmdq *cmdq;

	struct nvkm_falcon_msgq *msgq;

	struct nvkm_msgqueue *queue;



	struct work_struct work;

	bool initmsg_received;

};



int gp102_sec2_new(struct nvkm_device *, int, struct nvkm_sec2 **);

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